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    DELAY LOCKED LOOP CIRCUIT
    1.
    发明专利
    DELAY LOCKED LOOP CIRCUIT 失效

    公开(公告)号：JP2000357963A

    公开(公告)日：2000-12-26

    申请号：JP2000118392

    申请日：2000-04-19

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： DORTU JEAN-MARC ,  CHU ALBERT M ,  FERRAIOLO FRANK

    IPC: G06F1/10 ,  H03K5/14 ,  H03L7/00 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081

    Abstract: PROBLEM TO BE SOLVED: To obtain a delay element including a delay locked loop(DLL), where a follow-up ability with respect to delay which occurs in a circuit is improved. SOLUTION: A delay locked loop circuit 100 is provided with a delay line 112, the delay element 110 and a phase comparator 114. In this case, the circuit is constituted, in such a way that the delay line 112 generates delay in accordance with a control signal and is connected to an input node and an output node, that the delay element 110 is connected to the input node, gives a prescribed delay value to an input signal from the input node and supplied the delayed input signal is supplied and that the phase comparator 114 is connected to the output node and the delay element 110, compares the phase of the output signal with that of the delayed input signal, and outputs the control signal to the delay line 112 so that the line 112 gives the prescribed delay value to a part between the input node and the output node by the control signal.

    FREQUENCY RANGE TRIMMING FOR DELAY LINE
    2.
    发明专利
    FREQUENCY RANGE TRIMMING FOR DELAY LINE 失效

    公开(公告)号：JP2000357954A

    公开(公告)日：2000-12-26

    申请号：JP2000082458

    申请日：2000-03-23

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： DORTU JEAN-MARC ,  CHU ALBERT M ,  MILLER CHRISTOPHER P

    IPC: G06F1/10 ,  G11C8/00 ,  H03K5/13 ,  H03K5/14 ,  H03L7/00 ,  H03L7/081

    Abstract: PROBLEM TO BE SOLVED: To provide a device for trimming a frequency range with respect to a data path through the use of a delay lock loop circuit. SOLUTION: A delay line is formed of a plurality of delay elements 112 connected to an input side and an output side and a voltage device 116 which controls power to the plurality of delay elements. The delay elements 112 form a delay, which is to be given to signals passing through the delay elements 112. The voltage device 116 supplies at least one prescribed voltage to the delay elements 112, and delay in the delay elements 112 can be adjusted so that the delay is changed in accordance with at least one prescribed voltage. The delay line can be used in a delay lock loop, a clock circuit or other circuits.

    CIRCUIT AND METHOD FOR DATA CLOCK WAITING TIME COMPENSATION FOR DDR TIMING
    4.
    发明专利
    CIRCUIT AND METHOD FOR DATA CLOCK WAITING TIME COMPENSATION FOR DDR TIMING 失效

    公开(公告)号：JP2000187522A

    公开(公告)日：2000-07-04

    申请号：JP15986599

    申请日：1999-06-07

    Applicant: SIEMENS AG ,  IBM

    Inventor： DORTU JEAN-MARC ,  CHU ALBERT M

    IPC: G06F1/06 ,  G11C7/00 ,  G11C11/407 ,  H03L7/00 ,  H03L7/081 ,  H04L7/02

    Abstract: PROBLEM TO BE SOLVED: To provide a compensating method for a clock for a data waiting time which is suitable to a double-data-rate application by allowing a phase comparator to control a delay line circuit in relation to the phase shift detection between a 1st and a 2nd clock signal, and a time shift signal. SOLUTION: A receiver 6 receives a system clock signal CLK and generates clock signals CLK1 and CLK2 respectively. The clock signals are inputted to the input sides of delay lines 4 and 5. The delay lines 4 and 5 form a delay locked loop with a phase comparator 2. This delay circuit is able to receive the 1st and 2nd clock signals CLK1 and CLK2 and send time shift clock signals corresponding to the clock signals CLK1 and CLK2 and include the phase comparator 2. The phase comparator 2 controls the delay line circuit in relation to the phase shift detection between the clock signals CLK1 and CLK2 and time shift signals CLK1' and CLK2' corresponding to the clock signals CLK1 and CLK2.

    7.
    发明专利
    未知

    公开(公告)号：DE60027065T2

    公开(公告)日：2006-10-05

    申请号：DE60027065

    申请日：2000-01-21

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： CHU ALBERT M ,  FIFIELD JOHN A ,  ROTELLA JASON E ,  DORTU JEAN-MARC

    IPC: H03K5/15 ,  H03L7/081 ,  G11C7/22 ,  H03L7/095

    Abstract: A circuit and method are provided wherein a receiver receives an input train of pulses. The circuit includes a delay-locked-loop coupled to an output of the receiver. The delay-locked-loop includes a pulse generator responsive to received input train of pulses produced at the output of the receiver for producing first pulses in response to the leading edges of the received input train of pulses and second pulses in response to the trailing edges of received input train of pulses. The leading edge of the first pulse has the same edge type as the leading edge of the second pulse (i.e., the leading edge of the first pulse and the leading edge of the second pulse are either both rising edge types or both falling edges types). The first pulses and the second pulses are combined into a composite input signal comprising the first and second pulses with the leading edge of the first pulse maintaining the same edge type. The delay-locked-loop also includes a variable delay line fed by the composite input signal for producing a composite output train of pulses comprising both the first train of pulses and the second train of pulses after a selected time delay provided by the delay line. The delay-locked-loop is responsive to one of the first train of pulses and the second train of pulses in the composite output train of pulses for selecting the time delay of the variable delay line so as to produce the composite output train of pulses with a predetermined phase relationship to the input train of pulses.

    8.
    发明专利
    未知

    公开(公告)号：DE60027065D1

    公开(公告)日：2006-05-18

    申请号：DE60027065

    申请日：2000-01-21

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： CHU ALBERT M ,  FIFIELD JOHN A ,  ROTELLA JASON E ,  DORTU JEAN-MARC

    IPC: H03K5/15 ,  H03L7/081 ,  G11C7/22 ,  H03L7/095

    Abstract: A circuit and method are provided wherein a receiver receives an input train of pulses. The circuit includes a delay-locked-loop coupled to an output of the receiver. The delay-locked-loop includes a pulse generator responsive to received input train of pulses produced at the output of the receiver for producing first pulses in response to the leading edges of the received input train of pulses and second pulses in response to the trailing edges of received input train of pulses. The leading edge of the first pulse has the same edge type as the leading edge of the second pulse (i.e., the leading edge of the first pulse and the leading edge of the second pulse are either both rising edge types or both falling edges types). The first pulses and the second pulses are combined into a composite input signal comprising the first and second pulses with the leading edge of the first pulse maintaining the same edge type. The delay-locked-loop also includes a variable delay line fed by the composite input signal for producing a composite output train of pulses comprising both the first train of pulses and the second train of pulses after a selected time delay provided by the delay line. The delay-locked-loop is responsive to one of the first train of pulses and the second train of pulses in the composite output train of pulses for selecting the time delay of the variable delay line so as to produce the composite output train of pulses with a predetermined phase relationship to the input train of pulses.

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