公开(公告)号：DE10215666A1

公开(公告)日：2002-11-07

申请号：DE10215666

申请日：2002-04-09

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS ,  MALIK RAIEEV ,  DIVAKARUNI RAMA ,  MANDELMAN JACK A ,  JAIPRAKASH V C

IPC: H01L21/316 ,  H01L21/318 ,  H01L21/8242

Abstract: A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.

公开(公告)号：WO0247159A2

公开(公告)日：2002-06-13

申请号：PCT/US0143959

申请日：2001-11-14

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： JAIPRAKASH V C ,  SEITZ MICHEL ,  ARNOLD NORBERT

IPC: H01L21/8242

CPC classification number: H01L27/10867

Abstract: A semiconductor Dynamic Random Access Memory DRAM cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation STI region 480 is used as a masking region to confine the channel region of the access transistor, the first and second 433-1 output regions of the access transistor, and a strap region 448-1 connecting the second output region to the storage capacitor 440-1 , to a narrow portion of the trench. The so confined second output region of the access transistor has reduced leakage to similar second output regions of adjacent memory cells. Adjacent memory cells can then be placed closer to one another without an increase in leakage and cross-talk between adjacent memory cells.

Abstract translation: 使用垂直存取晶体管和形成在垂直沟槽中的存储电容器制造半导体动态随机存取存储器DRAM单元。 浅沟槽隔离STI区域480用作掩蔽区域，以将存取晶体管的沟道区域，存取晶体管的第一和第二433-1输出区域以及将第二输出区域连接到的带区域448-1 存储电容器440-1到沟槽的窄部分。 存取晶体管的如此限制的第二输出区域减少了泄漏到相邻存储器单元的类似的第二输出区域。 相邻的存储器单元然后可以彼此更靠近地放置，而不会增加相邻存储单元之间的泄漏和串扰。