公开(公告)号：WO02086904A2

公开(公告)日：2002-10-31

申请号：PCT/US0210892

申请日：2002-04-08

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUDELKA STEPHAN P ,  JAIPRAKASH VENKATACHAIAM C ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242 ,  G11C11/00

CPC classification number: H01L27/10864 ,  H01L27/10876 ,  H01L27/10888

Abstract: A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.

Abstract translation: 存储单元的方法具有沟槽电容器和与电容器相邻的垂直晶体管。 垂直晶体管在沟槽电容器上方具有栅极导体。 栅极导体的上部比栅极导体的下部窄。 存储单元还包括邻近栅极导体的上部的间隔物和邻近栅极导体的位线接触。 间隔物减少了位线接触和栅极导体之间​​的短路。 栅极导体上方的栅极接触具有将栅极接触与位线分离的绝缘体。 栅极导体的上部和下部的宽度之间的差异减小了位线接触和栅极导体之间​​的短路。