公开(公告)号：JP2000251468A

公开(公告)日：2000-09-14

申请号：JP2000034052

申请日：2000-02-10

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： JI BRIAN ,  MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HANSON DAVID

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/409

Abstract: PROBLEM TO BE SOLVED: To increase data speed or band width by arranging a pre-fetch circuit so that data speed among each hierarchy stage is all equalized substantially and controlling a latch so that the respective data speed at each hierarchy stage is all maintained. SOLUTION: Stages A-C have different data speed/signal time (data speed/bit) a, b, c respectively. Data speed at each stage is determined by data speed/signal path (selected by the number of signal path that is the number of pre-fetch). Pre-fetch is constituted between stages A-B of m>=int(a/b), pre-fetch is constituted between stages B-C of n>=int(b/c), and integers m, n are adjusted as desired. In order to vary pre-fetch depth at each stage, a pointer is designed so as to correspond to pre-fetch depth. A pointer signal is supplied by using a control circuit 214, the control circuit 214 latches continuously data made to synchronize with the latch included in a pre-fetch circuit, and timing is performed optimally.

公开(公告)号：JP2000244471A

公开(公告)日：2000-09-08

申请号：JP2000035979

申请日：2000-02-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: H03K5/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4096 ,  H04J3/06 ,  H04L7/00 ,  H04L7/02 ,  H04L25/40

Abstract: PROBLEM TO BE SOLVED: To provide a synchronous data fetch circuit that synchronously captures data at a frequency substantially higher than a frequency of each data line and can use a step-down voltage signal. SOLUTION: The synchronous data fetch circuit 200 is provided with a timer generator 206 provided with a 1st timer generator output side, a 1st data driver circuit 210 consisting of a plurality of data drivers that receives a plurality of 1st data signals and a plurality of timing signals, and a 1st data clock circuit 214 that receives a data stream with a 1st high frequency and a 1st high frequency timing pulse stream. Thus, fetch of data in the 1st high frequency data stream is synchronized by using the 1st high frequency timing pulse stream and a synchronized data capture signal is outputted.

公开(公告)号：JP2000244470A

公开(公告)日：2000-09-08

申请号：JP2000035978

申请日：2000-02-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HANSON DAVID RUSSELL ,  MUELLER GERHARD

IPC: G11C11/413 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/417 ,  H03K5/00 ,  H04L7/00 ,  H04L7/02 ,  H04L25/40

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption and/or to improve performance by receiving the data signal and the timing signal of full swing as inputs, converting them into voltage levels that are stepped down and synchronizing the data/ timing signals with voltage level signals that are stepped down. SOLUTION: This data synchronization take-in circuit 200 can receive/output a full swing signal and synchronizes data take-in by generating and using a step-down signal. A timing driver circuit 202 receives a full swing timing signal by an input node 208. The timing driver circuit 202 not only adds delay required for taking in appropriate data in a reception circuit to the full swing timing signal but also shifts the voltage level of the timing signal and outputs the timing signal which is stepped down. The voltage level of the timing signal which is stepped down is stepped down and the stepped down level is lower than the voltage level of the full swing signal.

公开(公告)号：JP2000286693A

公开(公告)日：2000-10-13

申请号：JP2000063779

申请日：2000-03-08

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/41 ,  G11C11/417 ,  H03K19/017 ,  H03K19/0175

Abstract: PROBLEM TO BE SOLVED: To provide an improved driver circuit which can increase a charge rate to attain an operation faster than an IC by increasing the current of the driver output and operating the driver circuit in an increased overdrive mode. SOLUTION: An overdrive sub-circuit 240 includes an overdrive output 248 which is connected to a driver input 273. The offset set to an active control output signal is supplied to the circuit 240 and the circuit 240 generates an active overdrive output signal to increase the level of overdrive voltage. The overdrive voltage represents the difference between the gate-source voltage and the threshold voltage of a driver transistor. The increased overdrive voltage results in the operation of the driver transistor in an increased overdrive mode, thus improving the performance of the driver transistor.

公开(公告)号：JP2000235793A

公开(公告)日：2000-08-29

申请号：JP2000000202

申请日：2000-01-05

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: G11C11/41 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C11/417 ,  H03K19/017

Abstract: PROBLEM TO BE SOLVED: To provide a driver circuit in which a charge rate is increased to operate a semiconductor device with a high clock cycle. SOLUTION: A memory chip has plural first sense amplifier 14. The plural first sense amplifiers 14 are multiplexed by MUX16 and connected to a second sense amplifier 24 through global data bus MDQ and bMDQ. The first sense amplifiers detect electric charges from a memory array cell of a memory array, the second sense amplifier 24 translates this charges to a higher level (DOUT), and this high level is expelled by an off-chip driver from a chip. A changing circuit 22 is connected to the global data bus MDQ and bMDQ, and comprises a driver circuit which can charge the global data bus with an increased rate.

公开(公告)号：WO0193273A3

公开(公告)日：2002-08-08

申请号：PCT/US0117441

申请日：2001-05-31

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  NETIS DMITRY

IPC: G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4094 ,  G11C11/4097 ,  G11C7/10

CPC classification number: G11C11/4094 ,  G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4097

Abstract: There is provided a semiconductor memory device that includes: a plurality of memory cells arranged in at least two groups (102); at least one sense amplifier (SA); a first and a second multiplexer (MUXs); and at least one programmable control device (control circuit). Each multiplexer is adapted to couple at least one of the groups to the amplifier. The programmable control device is adapted to control the first and said second multiplexers. In one embodiment, the programmable control device is adapted to control the multiplexers independently.

Abstract translation: 提供了一种半导体存储器件，其包括：布置在至少两组（102）中的多个存储单元; 至少一个读出放大器（SA）; 第一和第二多路复用器（MUX）; 和至少一个可编程控制装置（控制电路）。 每个多路复用器适于将至少一个组耦合到放大器。 可编程控制装置适于控制第一和第二多路复用器。 在一个实施例中，可编程控制装置适于独立地控制多路复用器。

公开(公告)号：WO0143135A9

公开(公告)日：2002-05-16

申请号：PCT/US0032921

申请日：2000-12-05

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HANSON DAVID R ,  KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  H03K17/22 ,  H03K19/0175

CPC classification number: G11C7/1072 ,  G11C7/1078

Abstract: A prefetch input write driver for a random access memory (RAM) and a RAM including the prefetch input write driver. The prefetch input write driver is especially for a synchronous dynamic RAM (SDRAM). The prefetch input write driver includes a data input stage receiving data, an enable stage receiving a corresponding data enable, and a write driver providing received data to a memory array in response to a write signal and the corresponding enable stage state. The data stage and the enable stage may each include two or more series connected three state drivers and a latch at the output of each three state driver. As data passes through the data stage a corresponding enable state is passed through the enable stage. Data is passed to the RAM array if the enable state indicates that data in the data stage is to be written into the array.

Abstract translation: 用于随机存取存储器（RAM）的预取输入写入驱动器和包括预取输入写入驱动器的RAM。 预取输入写入驱动器特别适用于同步动态RAM（SDRAM）。 预取输入写入驱动器包括数据输入级接收数据，使能级接收对应的数据使能，以及写入驱动器，响应于写入信号和相应的使能级状态向存储器阵列提供接收到的数据。 数据级和使能级可以各自包括两个或更多个串联连接的三状态驱动器和每个三状态驱动器的输出端的锁存器。 当数据通过数据阶段时，相应的使能状态通过使能阶段。 如果使能状态指示要将数据级中的数据写入阵列，则将数据传递到RAM阵列。

公开(公告)号：WO02054405A8

公开(公告)日：2002-09-06

申请号：PCT/US0147378

申请日：2001-12-04

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C7/12 ,  G11C

CPC classification number: G11C7/12

Abstract: A bitline architecture having bitlines with electrically controllable bitline lengths is described. The bitlines are provided with a switch which selectively couples or decouples local bitline segments of a bitline, depending on the need to execute the memory access. Bitlines with controllable bitline lengths can result in a reduction in power consumption without additional sense amplifiers or an additional metal layer.

Abstract translation: 描述了具有电可控位线长度的位线的位线架构。 位线提供有根据执行存储器访问的需要选择性地耦合或解耦位线的局部位线段的开关。 具有可控位线长度的位线可以导致功耗的降低，而不需要附加的读出放大器或额外的金属层。

公开(公告)号：WO0156031A3

公开(公告)日：2002-03-07

申请号：PCT/US0102610

申请日：2001-01-26

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MUELLER GERHARD ,  HANSON DAVID R

IPC: H03K19/0175 ,  B24B9/06 ,  B24B37/04 ,  G11C5/06 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/094

CPC classification number: B24B9/065 ,  B24B37/04 ,  G11C5/063 ,  H03K19/0013 ,  H03K19/018592 ,  H03K19/09429

Abstract: A bidirectional full swing voltage repeater implemented on a signal line of an integrated circuit, which includes a first enable node for providing a first enable signal and a second enable node for providing a second enable signal. There is included a first full-swing unidirectional repeater circuit coupled between a first portion of the signal line and a second portion of the signal line. The first full-swing unidirectional repeater is configured to pass a first full swing signal from the first portion of the signal line to the second portion of the signal line when the first enable signal is enabled. The second full-swing unidirectional repeater circuit is coupled between the first portion of the signal line and the second portion of the signal line. The second full-swing unidirectional repeater circuit is configured to pass a second full swing signal from the second portion of the signal line to the first portion of the signal line when the second enable signal is enabled, wherein the first full-swing unidirectional repeater circuit and the second full-swing unidirectional repeater circuit are tri-stated when both the first enable signal and the second enable signal are disabled.

Abstract translation: 在集成电路的信号线上实现的双向全摆幅电压中继器，其包括用于提供第一使能信号的第一使能节点和用于提供第二使能信号的第二使能节点。 包括耦合在信号线的第一部分和信号线的第二部分之间的第一全方位单向中继器电路。 第一全方位单向中继器被配置为当第一使能信号被使能时，将第一全摆幅信号从信号线的第一部分传递到信号线的第二部分。 第二全方位单向中继器电路耦合在信号线的第一部分和信号线的第二部分之间。 第二全方位单向中继器电路被配置为当第二使能信号被使能时，将第二全摆幅信号从信号线的第二部分传递到信号线的第一部分，其中第一全方位单向中继器电路 而当第一使能信号和第二使能信号都被禁止时，第二全方位单向中继器电路是三态的。

公开(公告)号：WO0156032A3

公开(公告)日：2001-12-13

申请号：PCT/US0102620

申请日：2001-01-26

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: H03K19/0175 ,  B24B9/06 ,  B24B37/04 ,  G11C5/06 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/017

CPC classification number: B24B9/065 ,  B24B37/04 ,  G11C5/063 ,  H03K19/0013 ,  H03K19/018592 ,  H03K19/09429

Abstract: A method in an integrated circuit for implementing a reduced voltage repeater circuit on a signal line having thereon reduced voltage signals. The reduced voltage signals has a voltage level that is below VDD. The reduced voltage repeater circuit is configured to be coupled to the signal line and having an input node coupled to a first portion of the signal line for receiving a first reduced voltage signal and an output node coupled to a second portion of the signal line for outputting a second reduced voltage signal. The method includes coupling the input node to the first portion of the signal line. The input node is coupled to an input stage of the reduced voltage repeater circuit. The input stage is configured to receive the first reduced voltage signal on the signal line. The input stage is also coupled to a level shifter stage that is arranged to output a set of level shifter stage control signals responsive to the first reduced voltage signal. A voltage range of the set of level shifter stage control signals is higher than a voltage range associated with the first reduced voltage signal. There is further included coupling the output node to the second portion of the signal line. The output node also is coupled to an output stage of the reduced voltage repeater circuit. The output stage is configured to output the second reduced voltage signal on the output node responsive to the set of level shifter stage control signals. A voltage range of the second reduced voltage signal is lower than the voltage range of the set of level shifter stage control signals.

Abstract translation: 一种集成电路中用于在其上具有降低的电压信号的信号线上实现降低电压转发器电路的方法。 降低的电压信号具有低于VDD的电压电平。 降低电压转发器电路被配置为耦合到信号线并且具有耦合到信号线的第一部分以用于接收第一降低的电压信号的输入节点以及耦合到信号线的第二部分以用于输出 第二降低电压信号。 该方法包括将输入节点耦合到信号线的第一部分。 输入节点耦合到降压转发器电路的输入级。 输入级被配置为在信号线上接收第一降低电压信号。 输入级还耦合到电平移位器级，该电平移位器级被布置为响应于第一降低的电压信号而输出一组电平移位器级控制信号。 该组电平移位器级控制信号的电压范围高于与第一降低电压信号相关联的电压范围。 还包括将输出节点耦合到信号线的第二部分。 输出节点还耦合到降压转发器电路的输出级。 输出级被配置为响应于该组电平移位器级控制信号在输出节点上输出第二降低电压信号。 第二降低电压信号的电压范围低于该组电平移位器控制信号的电压范围。