公开(公告)号：WO0201606A3

公开(公告)日：2002-05-30

申请号：PCT/US0120175

申请日：2001-06-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ALSMEIER JOHANN ,  RADEN CARL

IPC: H01L27/108

CPC classification number: H01L27/10841 ,  H01L27/10829

Abstract: A layout pattern for increasing the spacing between the deep trenches (79, 81) of one cell pair and the deep trenches of an adjacent cell pair in an array of semiconductor DRAM cell pairs each of which cell pairs share a common bitline contact (77) to bitlines (87, 89, 91) arranged in one direction and each of which cell pairs are coupled to gate conductors (83) arranged orthogonal to the bitlines. The layout pattern is formed by positioning the deep trenches of all of said pairs along alternate bitlines so they are offset from said bitlines along gate conductors in opposing directions. The deep trenches of all of the remaining bitlines are offset from said bitlines in opposing directions opposite to the opposing directions of said trenches along said alternate bitlines so as to form a herringbone pattern of cells.

Abstract translation: 一种用于增加一个单元对的深沟槽（79,81）和半导体DRAM单元对阵列中的相邻单元对的深沟槽之间的间隔的布局图案，每个单元对共享共同的位线触点（77） 到沿一个方向布置的位线（87,89,91），并且每个单元对耦合到与位线正交布置的栅极导体（83）。 通过将所有对的深沟槽沿着交替位线定位，使得它们沿相反方向沿着栅极导体偏离所述位线而形成布局图案。 所有剩余位线的深沟槽在与所述沟槽沿着所述替代位线的相反方向相反的相对方向上偏离所述位线，以便形成单元格的人字形图案。