公开(公告)号：JP2002289701A

公开(公告)日：2002-10-04

申请号：JP2002016708

申请日：2002-01-25

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： YE QIUYI ,  TONTI WILLIAM R ,  LI YUJUN

IPC: H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49

Abstract: PROBLEM TO BE SOLVED: To provide a dual work function semiconductor structure having borderless contact, and to provide a method of fabricating the same. SOLUTION: This structure may include a field effect transistor (FET) having a substantially cap-free gate 108 and conductive contacts 134, 170 to a diffusion 116 adjacent to the cap-free gate, wherein the conductive contacts are borderless to the gate. Because this structure is the dual work function structure, the conductive contacts are allowed to extend over the cap-free gate without being electrically connected thereto.

公开(公告)号：DE10233234A1

公开(公告)日：2003-04-17

申请号：DE10233234

申请日：2002-07-22

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： YE QIUYI ,  TONTI WILLIAM ,  LI YUJUN ,  MANDELMAN JACK A

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78

Abstract: A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the MOSFET) or a silicon etch step (according to a second method of making the MOSFET). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. A suicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.

公开(公告)号：JP2007053400A

公开(公告)日：2007-03-01

申请号：JP2006289044

申请日：2006-10-24

Applicant: Infineon Technol North America Corp ,  Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  インフィニオン テクノロジーズ ノース アメリカ コーポレイション Infineon Technologies North America Corp.

Inventor： YE QIUYI ,  TONTI WILLIAM R ,  LI YUJUN

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L27/10888 ,  H01L21/76897 ,  H01L27/10894

Abstract: PROBLEM TO BE SOLVED: To provide a dual work function semiconductor structure with borderless contact and a method for manufacturing the same.
SOLUTION: The structure may comprise a substantially cap-free gate 108 and conductive contacts 134 and 170 to a diffusion part 116 adjacent to the cap-free gate, and the conductive contact may include a field effect transistor (FET) borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供具有无边界接触的双功能半导体结构及其制造方法。 解决方案：该结构可以包括基本无盖的栅极108和导电触点134和170，其连接到与无盖盖栅极相邻的扩散部分116，并且导电触点可以包括无边界的场效应晶体管（FET） 大门。 由于该结构是双重功能结构，所以允许导电接触件在无盖栅极上延伸而不与其电连接。 版权所有（C）2007，JPO＆INPIT