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公开(公告)号：US12260902B2
公开(公告)日：2025-03-25
申请号：US18042574
申请日：2020-08-24
Inventor： Qing Luo , Bing Chen , Hangbing Lv , Ming Liu , Cheng Lu
IPC: G11C7/22 , G11C11/408 , G11C11/4094 , G11C11/4096 , H03K19/017
Abstract: A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.
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公开(公告)号：US12205630B2
公开(公告)日：2025-01-21
申请号：US18005101
申请日：2020-08-24
Inventor： Qing Luo , Bing Chen , Hangbing Lv , Ming Liu , Cheng Lu
IPC: G11C11/4096 , G11C11/408 , G11C11/4094 , H03K19/017
Abstract: Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.
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