公开(公告)号：US20200176674A1

公开(公告)日：2020-06-04

申请号：US16786346

申请日：2020-02-10

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Qing Luo ,  Hangbing Lv ,  Ming Liu ,  Xiaoxin Xu ,  Cheng Lu

IPC: H01L45/00

Abstract: The present disclosure provides a 1S1R memory integrated structure and a method for fabricating the same, wherein the 1S1R memory integrated structure includes: a word line metal, a resistive material layer, a selector lower electrode, a selector material layer, a selector upper electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the selector upper electrode is formed in the groove. According to the 1S1R memory integrated structure and its fabricating method in the present disclosure, by the change of the integrated position of the selector, the device area of the selector is much larger than the device area of the memory, which significantly reduces the requirement for the on-state current density of the selector.

公开(公告)号：US20210296579A1

公开(公告)日：2021-09-23

申请号：US17250553

申请日：2018-08-02

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Qi Liu ,  Hangbing Lv ,  Ming Liu ,  Xiaoxin Xu ,  Cheng Lu ,  Shengjie Zhao

IPC: H01L45/00

Abstract: The present disclosure discloses a resistive random access memory, and the resistive random access memory includes a lower electrode layer, a ferroelectric material layer, and an upper electrode layer arranged in sequence from bottom to top, wherein the ferroelectric material layer includes a doped HfO2 ferroelectric thin film.

公开(公告)号：US12260902B2

公开(公告)日：2025-03-25

申请号：US18042574

申请日：2020-08-24

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Qing Luo ,  Bing Chen ,  Hangbing Lv ,  Ming Liu ,  Cheng Lu

IPC: G11C7/22 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096 ,  H03K19/017

Abstract: A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

公开(公告)号：US11205750B2

公开(公告)日：2021-12-21

申请号：US16786346

申请日：2020-02-10

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Qing Luo ,  Hangbing Lv ,  Ming Liu ,  Xiaoxin Xu ,  Cheng Lu

IPC: H01L45/00 ,  G11C13/00

Abstract: The present disclosure provides a 1S1R memory integrated structure and a method for fabricating the same, wherein the 1S1R memory integrated structure includes: a word line metal, a resistive material layer, a selector lower electrode, a selector material layer, a selector upper electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the selector upper electrode is formed in the groove. According to the 1S1R memory integrated structure and its fabricating method in the present disclosure, by the change of the integrated position of the selector, the device area of the selector is much larger than the device area of the memory, which significantly reduces the requirement for the on-state current density of the selector.

公开(公告)号：US12293781B2

公开(公告)日：2025-05-06

申请号：US18261716

申请日：2021-01-21

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huai Lin ,  Guozhong Xing ,  Zuheng Wu ,  Long Liu ,  Di Wang ,  Cheng Lu ,  Peiwen Zhang ,  Changqing Xie ,  Ling Li ,  Ming Liu

IPC: G11C11/16

Abstract: The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.

公开(公告)号：US12205630B2

公开(公告)日：2025-01-21

申请号：US18005101

申请日：2020-08-24

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qing Luo ,  Bing Chen ,  Hangbing Lv ,  Ming Liu ,  Cheng Lu

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094 ,  H03K19/017

Abstract: Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.