公开(公告)号：US20220389591A1

公开(公告)日：2022-12-08

申请号：US17891025

申请日：2022-08-18

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong ZHU ,  Xiaogen YIN ,  Chen LI ,  Anyan DU ,  Yongkui ZHANG

IPC: C23F1/16 ,  H01L21/306

Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.

公开(公告)号：US20220102559A1

公开(公告)日：2022-03-31

申请号：US17427539

申请日：2019-04-24

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU ,  Chen LI ,  Yongkui ZHANG

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66

Abstract: Disclosed are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. The semiconductor device may include: a substrate; an active region extending vertically on the substrate, wherein the active region includes a first source/drain layer, a channel layer and a second source/drain layer that are sequentially stacked; a gate stack formed around at least part of an outer peripheral sidewall of the channel layer. A sidewall of the gate stack close to the channel layer is aligned with the outer peripheral sidewall of the channel layer, so as to occupy substantially a same range in a vertical direction, and a part of the gate stack close to the channel layer has a shape that gradually tapers as getting close to the channel layer.

公开(公告)号：US20240021483A1

公开(公告)日：2024-01-18

申请号：US18477004

申请日：2023-09-28

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong ZHU ,  Yongkui ZHANG ,  Xiaogen YIN ,  Chen LI ,  Yongbo LIU ,  Kunpeng JIA

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/0925 ,  H01L21/823842

Abstract: The disclosed technology provides a semiconductor device, a manufacturing method thereof, and an electronic device including the device. An example semiconductor device includes a substrate; a first device and a second device on the substrate. Each of the first device and the second device include a first source/drain layer, a channel layer, and a second source layer that are sequentially stacked, from bottom to top, on the substrate, and a gate stack around at least a part of an outer periphery of the channel layer, with sidewalls of the respective channel layers of the first device and the second device extending at least partially along different crystal planes or crystal plane families.

公开(公告)号：US20230163204A1

公开(公告)日：2023-05-25

申请号：US17919652

申请日：2021-03-23

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU ,  Chen LI

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/0676 ,  H01L29/6653 ,  H01L29/66545

Abstract: Disclosed are a semiconductor device having a U-shaped structure, a method of manufacturing the semiconductor device, and an electronic including the semiconductor device. According to an embodiment, the semiconductor device may include: a first fin and a second fin disposed opposite to each other, wherein the first fin and the second fin extend in a vertical direction with respect to a substrate; a connection nanosheet connecting a bottom end of the first fin to a bottom end of a second fin to form a U-shaped structure, wherein the connection nanosheet is spaced apart from a top surface of the substrate.

公开(公告)号：US20210222303A1

公开(公告)日：2021-07-22

申请号：US16962084

申请日：2018-09-21

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong ZHU ,  Xiaogen YIN ,  Chen LI ,  Anyan DU ,  Yongkui ZHANG

IPC: C23F1/16 ,  H01L21/306

Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.