公开(公告)号：US20210193533A1

公开(公告)日：2021-06-24

申请号：US17250770

申请日：2018-10-31

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong ZHU ,  Yongkui ZHANG ,  Xiaogen YIN ,  Chen Li ,  Yongbo LIU ,  Kunpeng JIA

IPC: H01L21/8238 ,  H01L27/092

Abstract: The disclosed technology provides a semiconductor device, a manufacturing method thereof, and an electronic device including the device. An example semiconductor device includes a substrate; a first device and a second device on the substrate. Each of the first device and the second device include a first source/drain layer, a channel layer, and a second source layer that are sequentially stacked, from bottom to top, on the substrate, and a gate stack around at least a part of an outer periphery of the channel layer, with sidewalls of the respective channel layers of the first device and the second device extending at least partially along different crystal planes or crystal plane families.

公开(公告)号：US20220102559A1

公开(公告)日：2022-03-31

申请号：US17427539

申请日：2019-04-24

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU ,  Chen LI ,  Yongkui ZHANG

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66

Abstract: Disclosed are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. The semiconductor device may include: a substrate; an active region extending vertically on the substrate, wherein the active region includes a first source/drain layer, a channel layer and a second source/drain layer that are sequentially stacked; a gate stack formed around at least part of an outer peripheral sidewall of the channel layer. A sidewall of the gate stack close to the channel layer is aligned with the outer peripheral sidewall of the channel layer, so as to occupy substantially a same range in a vertical direction, and a part of the gate stack close to the channel layer has a shape that gradually tapers as getting close to the channel layer.

公开(公告)号：US20210222303A1

公开(公告)日：2021-07-22

申请号：US16962084

申请日：2018-09-21

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong ZHU ,  Xiaogen YIN ,  Chen LI ,  Anyan DU ,  Yongkui ZHANG

IPC: C23F1/16 ,  H01L21/306

Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.

公开(公告)号：US20240021483A1

公开(公告)日：2024-01-18

申请号：US18477004

申请日：2023-09-28

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong ZHU ,  Yongkui ZHANG ,  Xiaogen YIN ,  Chen LI ,  Yongbo LIU ,  Kunpeng JIA

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/0925 ,  H01L21/823842

Abstract: The disclosed technology provides a semiconductor device, a manufacturing method thereof, and an electronic device including the device. An example semiconductor device includes a substrate; a first device and a second device on the substrate. Each of the first device and the second device include a first source/drain layer, a channel layer, and a second source layer that are sequentially stacked, from bottom to top, on the substrate, and a gate stack around at least a part of an outer periphery of the channel layer, with sidewalls of the respective channel layers of the first device and the second device extending at least partially along different crystal planes or crystal plane families.

公开(公告)号：US20230187497A1

公开(公告)日：2023-06-15

申请号：US17925913

申请日：2021-03-18

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU ,  Xuezheng AI ,  Yongkui ZHANG

IPC: H01L29/06 ,  H01L29/786 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L29/78696 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor apparatus having a staggered structure, a method of manufacturing a semiconductor apparatus, and an electronic device including the semiconductor apparatus. The semiconductor apparatus includes a first element and a second element on a substrate. The first element and the second element each include a comb-shaped structure. The comb-shaped structure includes a first portion extending in a vertical direction relative to the substrate, and at least one second portion extending from the first portion in a lateral direction relative to the substrate and spaced from the substrate. A height of the second portion of the first element in the vertical direction is staggered with respect to a height of the second portion of the second element in the vertical direction. A material of the comb-shaped structure of the first element is different from a material of the comb-shaped structure of the second element.

公开(公告)号：US20220389591A1

公开(公告)日：2022-12-08

申请号：US17891025

申请日：2022-08-18

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong ZHU ,  Xiaogen YIN ,  Chen LI ,  Anyan DU ,  Yongkui ZHANG

IPC: C23F1/16 ,  H01L21/306

Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.

公开(公告)号：US20160087062A1

公开(公告)日：2016-03-24

申请号：US14688523

申请日：2015-04-16

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang YIN ,  Yongkui ZHANG ,  Zhiguo ZHAO ,  Zhiyong LU ,  Huilong ZHU

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/4916 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes: a plurality of fin structures extending on a substrate along a first direction; a gate stack structure extending on the substrate along a second direction and across the plurality of fin structures, wherein the gate stack structure includes a gate conductive layer and a gate insulating layer, and the gate conductive layer is formed by a doped poly-semiconductor; trench regions in the plurality of fin structures and beneath the gate stack structure; and source/drain regions on the plurality of fin structures and at both sides of the gate stack structure along the first direction.

Abstract translation: 半导体器件包括：沿着第一方向在衬底上延伸的多个翅片结构; 栅极堆叠结构，其沿着第二方向延伸并且跨越所述多个鳍状结构，其中所述栅极堆叠结构包括栅极导电层和栅极绝缘层，并且所述栅极导电层由掺杂的多晶半导体形成; 多个翅片结构中的沟槽区域和栅极堆叠结构下方的沟槽区域; 以及多个鳍结构上的源/漏区，以及沿着第一方向的栅叠层结构的两侧。