公开(公告)号：US20240021483A1

公开(公告)日：2024-01-18

申请号：US18477004

申请日：2023-09-28

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong ZHU ,  Yongkui ZHANG ,  Xiaogen YIN ,  Chen LI ,  Yongbo LIU ,  Kunpeng JIA

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/0925 ,  H01L21/823842

Abstract: The disclosed technology provides a semiconductor device, a manufacturing method thereof, and an electronic device including the device. An example semiconductor device includes a substrate; a first device and a second device on the substrate. Each of the first device and the second device include a first source/drain layer, a channel layer, and a second source layer that are sequentially stacked, from bottom to top, on the substrate, and a gate stack around at least a part of an outer periphery of the channel layer, with sidewalls of the respective channel layers of the first device and the second device extending at least partially along different crystal planes or crystal plane families.

公开(公告)号：US20150318356A1

公开(公告)日：2015-11-05

申请号：US14651980

申请日：2014-03-18

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Kunpeng JIA ,  Yajuan SU ,  Huilong ZHU ,  Chao ZHAO

IPC: H01L29/16 ,  H01L29/167 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/45 ,  H01L21/04 ,  H01L21/426 ,  H01L21/441 ,  H01L21/477 ,  H01L29/24 ,  H01L21/283

CPC classification number: H01L29/1606 ,  H01L21/0415 ,  H01L21/043 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/283 ,  H01L21/28512 ,  H01L21/28568 ,  H01L21/324 ,  H01L21/426 ,  H01L21/441 ,  H01L21/477 ,  H01L29/16 ,  H01L29/167 ,  H01L29/24 ,  H01L29/45

Abstract: A method and an arrangement for reducing a contact resistance of a two-dimensional crystal material are provided. An example method may include forming a contact material layer on a two-dimensional crystal material layer; performing ion implantation; and performing thermal annealing.

Abstract translation: 提供了用于降低二维晶体材料的接触电阻的方法和装置。 示例性方法可以包括在二维晶体材料层上形成接触材料层; 进行离子注入; 并进行热退火。

公开(公告)号：US20210193533A1

公开(公告)日：2021-06-24

申请号：US17250770

申请日：2018-10-31

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong ZHU ,  Yongkui ZHANG ,  Xiaogen YIN ,  Chen Li ,  Yongbo LIU ,  Kunpeng JIA

IPC: H01L21/8238 ,  H01L27/092

Abstract: The disclosed technology provides a semiconductor device, a manufacturing method thereof, and an electronic device including the device. An example semiconductor device includes a substrate; a first device and a second device on the substrate. Each of the first device and the second device include a first source/drain layer, a channel layer, and a second source layer that are sequentially stacked, from bottom to top, on the substrate, and a gate stack around at least a part of an outer periphery of the channel layer, with sidewalls of the respective channel layers of the first device and the second device extending at least partially along different crystal planes or crystal plane families.

公开(公告)号：US20170263452A1

公开(公告)日：2017-09-14

申请号：US15261068

申请日：2016-09-09

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yajuan SU ,  Kunpeng JIA ,  Chao ZHAO ,  Jun ZHAN ,  Heshi CAO

IPC: H01L21/02 ,  H01L21/4757 ,  H01L21/311

CPC classification number: H01L21/02527 ,  H01L21/0243 ,  H01L21/02521 ,  H01L21/02568 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/02658 ,  H01L21/31111 ,  H01L21/47573

Abstract: A method for manufacturing a two-dimensional material structure and a resultant two-dimensional material device. The method comprises steps of: forming a sacrificial FIN structure on a substrate; covering the sacrificial FIN structure with a dielectric; releasing the sacrificial FIN structure; forming a carrier FIN structure at a position for releasing the sacrificial FIN; and self-restrictedly growing two-dimensional material structure by taking the carrier FIN structure as a substrate. Utilizing the sacrificial FIN structure to implement self-restrictedly growing of the nanometer structure of the two-dimensional material results in a high precision, lower edge roughness, high yields and low process deviation as well as compatibility with the processing of CMOS large scale integrated circuits, making the method suitable for a large scale production of the two-dimensional material and related devices.