公开(公告)号：US20180197993A1

公开(公告)日：2018-07-12

申请号：US15849217

申请日：2017-12-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jun LUO ,  Chao ZHAO ,  Shi LIU

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/167 ,  H01L29/66 ,  H01L21/311 ,  H01L21/265 ,  H01L21/285 ,  H01L21/321

CPC classification number: H01L29/7851 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795

Abstract: The present invention relates to a semiconductor device and a method of manufacturing the same. There is provided a semiconductor device comprising: a semiconductor substrate with a fin; a gate intersecting with the fin and a source region and a drain region within the fin at both sides of the gate; metal silicides formed at the source region and the drain region and in contact with the source region and the drain region respectively; wherein there is a impurity dopant at a interface of the metal silicide in contact with the source/drain region, which is capable of reducing a Schottky barrier height between the metal silicide and the source/drain region. The provided semiconductor device can reduce the Schottky barrier height between the metal silicide and the source/drain region, thereby reducing the specific resistance of the contact.

公开(公告)号：US20150332973A1

公开(公告)日：2015-11-19

申请号：US14652956

申请日：2013-07-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huicai ZHONG ,  Qingqing LIANG ,  Da YANG ,  Chao ZHAO

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088 ,  H01L21/265 ,  H01L29/423

CPC classification number: H01L21/823437 ,  H01L21/26533 ,  H01L21/28176 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/78

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) forming gate lines extending in a direction on a substrate; b) forming a photoresist layer that covers the semiconductor structure; patterning the photoresist layer to form openings across the gate lines; c) narrowing the openings by forming a self-assembly copolymer inside the openings; and d) cutting the gate lines via the openings to make the gate lines insulated at the openings. Through forming an additional layer on the inner wall of the openings of the photoresist layer, the method for manufacturing a semiconductor structure provided by the present invention manages to reduce the distance between the two opposite walls of the openings in the direction of gate width, namely, the method manages to reduce the distance between the ends of electrically isolated gates located on the same line where it is unnecessary to manufacture a cut mask whose lines are extremely fine. Working area is therefore saved, which accordingly improves integration level of semiconductor devices. In addition, the present invention further provides a semiconductor structure according to the method provided by the present invention.

Abstract translation: 本发明提供一种制造半导体结构的方法，其包括：a）形成沿衬底方向延伸的栅极线; b）形成覆盖半导体结构的光致抗蚀剂层; 图案化光致抗蚀剂层以在栅极线上形成开口; c）通过在开口内形成自组装共聚物来缩小开口; 以及d）经由所述开口切割所述栅极线以使所述栅极线在所述开口处绝缘。 通过在光致抗蚀剂层的开口的内壁上形成附加层，本发明提供的半导体结构的制造方法旨在减小开口方向的两个相对壁之间在栅极宽度方向上的距离，即 该方法旨在减少位于同一线路上的电隔离门的端部之间的距离，其中不需要制造线极细的切割掩模。 因此节省了工作区域，从而提高了半导体器件的集成度。 此外，本发明还提供根据本发明提供的方法的半导体结构。

公开(公告)号：US20180294342A1

公开(公告)日：2018-10-11

申请号：US15871690

申请日：2018-01-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jinjuan XIANG ,  Xiaolei WANG ,  Hong YANG ,  Shi LIU ,  Junfeng LI ,  Wenwu WANG ,  Chao ZHAO

IPC: H01L29/66 ,  H01L29/49 ,  H01L21/265

CPC classification number: H01L29/66545 ,  H01L21/265 ,  H01L29/4966

Abstract: The present disclosure provides a method for manufacturing a transistor having a gate with a variable work function, comprising: providing a semiconductor substrate; forming a dummy gate stack on the semiconductor substrate and performing ion implantation on an exposed area of the semiconductor substrate at both sides of the dummy gate stack to form source/drain regions; removing the dummy gate and annealing the source/drain regions; providing an atomic layer deposition reaction device; introducing a precursor source reactant into the atomic layer deposition reaction device; and controlling an environmental factor for the atomic layer deposition device to grow a work function metal layer. The present disclosure also provides a transistor having a gate with a variable work function. The present disclosure may adjust a variable work function, and may use the same material system to obtain an adjustable threshold voltage within an adjustable range.

公开(公告)号：US20170309736A1

公开(公告)日：2017-10-26

申请号：US15368098

申请日：2016-12-02

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Sen HUANG ,  Xinyu LIU ,  Xinhua WANG ,  Ke WEI ,  Qilong BAO ,  Wenwu WANG ,  Chao ZHAO

IPC: H01L29/778 ,  H01L29/20 ,  H01L21/306 ,  H01L29/15 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L29/7786 ,  H01L21/30621 ,  H01L29/1066 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/432 ,  H01L29/66462

Abstract: A GaN-based power electronic device and a method for manufacturing the same is provided. The GaN-based power electronic device comprising a substrate and an epitaxial layer over the substrate. The epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer. The superlattice structure layer is provided over the heterostructure layer, and the P-type cap layer is provided over the superlattice structure layer. By using this electronic device, gate voltage swing and safe gate voltage range of the GaN-based power electronic device manufactured on the basis of the P-type cap layer technique may be further extended, and dynamic characteristics of the device may be improved. Therefore, application process for the GaN-based power electronic device that is based on the P-type cap layer technique will be promoted.

公开(公告)号：US20170263452A1

公开(公告)日：2017-09-14

申请号：US15261068

申请日：2016-09-09

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yajuan SU ,  Kunpeng JIA ,  Chao ZHAO ,  Jun ZHAN ,  Heshi CAO

IPC: H01L21/02 ,  H01L21/4757 ,  H01L21/311

CPC classification number: H01L21/02527 ,  H01L21/0243 ,  H01L21/02521 ,  H01L21/02568 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/02658 ,  H01L21/31111 ,  H01L21/47573

Abstract: A method for manufacturing a two-dimensional material structure and a resultant two-dimensional material device. The method comprises steps of: forming a sacrificial FIN structure on a substrate; covering the sacrificial FIN structure with a dielectric; releasing the sacrificial FIN structure; forming a carrier FIN structure at a position for releasing the sacrificial FIN; and self-restrictedly growing two-dimensional material structure by taking the carrier FIN structure as a substrate. Utilizing the sacrificial FIN structure to implement self-restrictedly growing of the nanometer structure of the two-dimensional material results in a high precision, lower edge roughness, high yields and low process deviation as well as compatibility with the processing of CMOS large scale integrated circuits, making the method suitable for a large scale production of the two-dimensional material and related devices.

公开(公告)号：US20160163592A1

公开(公告)日：2016-06-09

申请号：US14943706

申请日：2015-11-17

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huicai ZHONG ,  Chao ZHAO ,  Huilong ZHU

IPC: H01L21/768

CPC classification number: H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/49827

Abstract: In a method for manufacturing a semiconductor, a Through Silicon Via (TSV) template wafer and production wafers form a sandwich structure, in which the TSV template wafer has TSV structures uniformly distributed therein, for providing electrical connection between the production wafers to form 3D interconnection. The TSV template wafer is obtained by thinning a semiconductor wafer, which facilitates reducing the difficulty in etching and filling. Connection parts are provided on the TSV template wafer, for convenience of interconnection between the overlying and underlying production wafers, which facilitates reducing the difficulty in alignment and improving the convenience of design of electrical connection for 3D devices.

Abstract translation: 在制造半导体的方法中，透明硅（TSV）模板晶片和生产晶片形成夹层结构，其中TSV模板晶片具有均匀分布在其中的TSV结构，用于在生产晶片之间提供电连接以形成3D互连 。 通过减薄半导体晶片获得TSV模板晶片，这有助于降低蚀刻和填充的难度。 在TSV模板晶片上提供连接部件，以方便上层和下面的生产晶圆之间的互连，这有助于降低对准难度，并提高3D设备电气连接设计的便利性。

公开(公告)号：US20210408118A1

公开(公告)日：2021-12-30

申请号：US17395795

申请日：2021-08-06

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU ,  Junjie LI ,  Chao ZHAO

IPC: H01L27/22 ,  H01L29/78 ,  H01L43/12 ,  H01L29/66

Abstract: A Magnetic Random Access Memory (MRAM), a method of manufacturing the same, and an electronic device including the same are provided. The MRAM includes a substrate, an array of memory cells arranged in rows and columns, bit lines, and word lines. The memory cells each include a vertical switch device and a magnetic tunnel junction on the switch device and electrically connected to a first terminal of the switch device. An active region of the switch device at least partially includes a single-crystalline semiconductor material. Each of the memory cell columns is disposed on a corresponding bit line, and a second terminal of each of the respective switch devices in the memory cell column is electrically connected to the corresponding bit line. Each of the word lines is electrically connected to a control terminal of the respective switch devices of the respective memory cells in a corresponding memory cell row.

公开(公告)号：US20170365482A1

公开(公告)日：2017-12-21

申请号：US15366499

申请日：2016-12-01

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES ,  JIANGNAN UNIVERSITY

Inventor： Yuqiang DING ,  Liyong DU ,  Yuxiang ZHANG ,  Chao ZHAO ,  Jinjuan XIANG

IPC: H01L21/285 ,  C23C16/18 ,  C23C16/455 ,  H01L21/768

CPC classification number: H01L21/28556 ,  C23C16/18 ,  C23C16/45525 ,  C23C16/45553 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/76879

Abstract: The present invention provides a method for growing ni-containing thin film with single atomic layer deposition technology, comprising steps of: A) placing a substrate in a reaction chamber, and under the vacuum condition, passing a gas-phase Ni source in a form of pulses into the reaction chamber for deposition to obtain a substrate deposited with the Ni source, the Ni source comprising a compound having a structure of Formula I; B) passing a gas-phase reducing agent in a form of pulses into the reaction chamber to reduce the Ni source deposited on the substrate, obtaining a substrate deposited with a Ni thin film. The application of the Ni source having a structure of Formula I in the single atomic layer deposition technology allows a Ni-containing deposition layer with good shape retention to be deposited and formed on a nano-sized semiconductor device.

公开(公告)号：US20170327944A1

公开(公告)日：2017-11-16

申请号：US15517651

申请日：2015-09-17

Applicant: JIANGNAN UNIVERSITY ,  INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yuqiang DING ,  Chao ZHAO ,  Chongying XU ,  Shuyan YANG ,  Jinjuan XIANG ,  Hongyan MIAO ,  Dawei WANG

IPC: C23C16/20 ,  C23C16/455 ,  C23C16/40 ,  C07F5/06 ,  C23C16/18 ,  C23C16/08 ,  C23C16/448

CPC classification number: C23C16/20 ,  C07F5/066 ,  C07F5/069 ,  C23C16/08 ,  C23C16/18 ,  C23C16/34 ,  C23C16/403 ,  C23C16/4482 ,  C23C16/45534 ,  C23C16/45553

Abstract: Provided is an aluminum precursor for thin-film deposition having a structure of formula (I) or (II), wherein R1, R2, R3, R4, R5, R6, and R7 each independently represent a hydrogen atom, C1˜C6 alkyl, halo-C1˜C6 alkyl, C2˜C5 alkenyl, halo-C2˜C5 alkenyl, C3˜C10 cycloalkyl, halo-C3˜C10 cycloalkyl, C6˜C10 aryl, halo-C6˜C10 aryl or —Si(R0)3, and wherein R0 is C1˜C6 alkyl or halo-C1˜C6 alkyl. According to the present invention, based on the interaction principle between molecules, aluminum precursors for thin-film deposition are provided, which have a good thermal stability, are not susceptible to decomposition and convenient for storage and transportation, have good volatility at a high temperature, and are excellent in film formation.

公开(公告)号：US20160211351A1

公开(公告)日：2016-07-21

申请号：US15001087

申请日：2016-01-19

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Guilei WANG ,  Hushan CUI ,  Huaxiang YIN ,  Junfeng LI ,  Chao ZHAO

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/67 ,  C30B25/16 ,  C30B25/08 ,  C30B25/12 ,  C30B25/14 ,  H01L21/306 ,  C23C16/02

CPC classification number: H01L29/66795 ,  C30B25/08 ,  C30B25/12 ,  C30B25/14 ,  C30B25/16 ,  C30B35/00 ,  H01L21/67167

Abstract: An apparatus and a method for epitaxially growing sources and drains of a FinFET device. The apparatus comprises: a primary chamber; a wafer-loading chamber; a transfer chamber provided with a mechanical manipulator for transferring the wafer; an etching chamber for removing a natural oxide layer on the surface of the wafer and provided with a graphite base for positioning the wafer; at least one epitaxial reaction chamber; a gas distribution device for supplying respective gases to the primary chamber, the wafer loading chamber, the transfer chamber, the etching chamber and the epitaxial reaction chamber; and a vacuum device. The wafer loading, transfer, etching, and epitaxial reaction chambers are all positioned within the primary chamber. The apparatus integrates the etching chamber and epitaxial reaction chamber to remove the natural oxide layer on the surface of the wafer in a condition of isolating water and oxygen before the epitaxial reaction has occurred.

Abstract translation: 一种用于外延生长FinFET器件的源极和漏极的装置和方法。 该装置包括：主室; 晶片加载室; 传送室，设置有用于传送晶片的机械操纵器; 用于去除晶片表面上的自然氧化物层并设置有用于定位晶片的石墨基底的蚀刻室; 至少一个外延反应室; 用于向主室，晶片装载室，传送室，蚀刻室和外延反应室供应各种气体的气体分配装置; 和真空装置。 晶片装载，转移，蚀刻和外延反应室都位于主室内。 在外延反应发生之前，在分离水和氧的条件下，将蚀刻室和外延反应室集成在晶片表面上去除天然氧化物层。