公开(公告)号：US20230371384A1

公开(公告)日：2023-11-16

申请号：US18250742

申请日：2020-10-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Ling Li ,  Xuewen Shi ,  Nianduan Lu ,  Congyan Lu ,  Di Geng ,  Xinlv Duan ,  Ming Liu

IPC: H10N30/074 ,  G01L1/16 ,  H10N30/067

CPC classification number: H10N30/074 ,  G01L1/16 ,  H10N30/067

Abstract: A pressure sensor based on zinc oxide nanowires and a method of manufacturing a pressure sensor based on zinc oxide nanowires are provided. The manufacturing method includes: manufacturing a bottom electrode on a substrate; manufacturing a seed layer on the bottom electrode; manufacturing a zinc oxide nanowire layer on the seed layer; manufacturing a support layer on the zinc oxide nanowire layer; and manufacturing a top electrode on the support layer.

公开(公告)号：US11430385B2

公开(公告)日：2022-08-30

申请号：US17053992

申请日：2018-08-02

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Di Geng ,  Yue Su ,  Ling Li ,  Nianduan Lu ,  Ming Liu

IPC: G09G3/3233 ,  G09G3/3291

Abstract: A pixel compensation circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and an organic light-emitting diode, each of the first transistor to the sixth transistor including a drain, a source and a gate.

公开(公告)号：US20240005077A1

公开(公告)日：2024-01-04

申请号：US18250461

申请日：2020-10-30

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Nianduan Lu ,  Ling Li ,  Wenfeng Jiang ,  Di GENG ,  Jiawei Wang ,  Ming Liu

IPC: G06F30/39 ,  G16C60/00

CPC classification number: G06F30/39 ,  G16C60/00 ,  H01L29/786

Abstract: A method of designing a thin film transistor device, including: calculating characteristic parameters of searched materials; screening the materials according to a characteristic parameter threshold to obtain first active layer materials; simulating the first active layer material as an active layer material in a thin film transistor device model to obtain a device characteristic of the thin film transistor device; screening the first active layer materials according to a device characteristic threshold to obtain second active layer materials; taking the second active layer material as the active layer material of the thin film transistor device to perform an experiment; and selecting another second active layer material to perform the experiment once again when an experiment result does not meet a preset requirement, and a design of the thin film transistor device is completed until the experiment result meets the preset requirement.

公开(公告)号：US20180366643A1

公开(公告)日：2018-12-20

申请号：US16064116

申请日：2016-08-12

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Nianduan Lu ,  Pengxiao Sun ,  Ling Li ,  Ming Iiu ,  Qi Liu ,  Hangbing Lv ,  Shibing Long

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00 ,  G01N25/20

CPC classification number: H01L45/128 ,  G01N25/20 ,  G11C7/04 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/00 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1293

Abstract: A method for evaluating the thermal effects of 3D RRAM arrays and reducing thermal crosstalk, including the following steps: Step 1: calculating the temperature distribution in the array through 3D Fourier heat conduction equation; Step 2, selecting a heat transfer mode; Step 3, selecting an appropriate array structure; Step 4, analyzing the effect of position of programming device in the array on the temperature; Step 5, analyzing the thermal crosstalk effect in the array; Step 6, evaluating thermal effects and thermal crosstalk; Step 7, changing the array structure or modify operating parameters based on the evaluation results to reduce the thermal crosstalk. According to the method of the present invention, the influence of the position of the device on the temperature is analyzed according to the heat transfer mode of the 3D RRAM array, the thermal effect and the thermal crosstalk are evaluated, and the appropriate array structure and operating parameters are selected according to the evaluation result, which effectively improves the thermal stability of the device.

公开(公告)号：US10418549B2

公开(公告)日：2019-09-17

申请号：US16064116

申请日：2016-08-12

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Nianduan Lu ,  Pengxiao Sun ,  Ling Li ,  Ming Liu ,  Qi Liu ,  Hangbing Lv ,  Shibing Long

IPC: H01L45/00 ,  G01N25/20 ,  G11C13/00 ,  H01L27/24 ,  G11C7/04

Abstract: A method for evaluating the thermal effects of 3D RRAM arrays and reducing thermal crosstalk, including the following steps: Step 1: calculating the temperature distribution in the array through 3D Fourier heat conduction equation; Step 2, selecting a heat transfer mode; Step 3, selecting an appropriate array structure; Step 4, analyzing the effect of position of programming device in the array on the temperature; Step 5, analyzing the thermal crosstalk effect in the array; Step 6, evaluating thermal effects and thermal crosstalk; Step 7, changing the array structure or modify operating parameters based on the evaluation results to reduce the thermal crosstalk. According to the method of the present invention, the influence of the position of the device on the temperature is analyzed according to the heat transfer mode of the 3D RRAM array, the thermal effect and the thermal crosstalk are evaluated, and the appropriate array structure and operating parameters are selected according to the evaluation result, which effectively improves the thermal stability of the device.