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1.发明公开公开(公告)号：US20230371384A1
公开(公告)日：2023-11-16
申请号：US18250742
申请日：2020-10-26
Inventor： Ling Li , Xuewen Shi , Nianduan Lu , Congyan Lu , Di Geng , Xinlv Duan , Ming Liu
IPC: H10N30/074 , G01L1/16 , H10N30/067
CPC classification number: H10N30/074 , G01L1/16 , H10N30/067
Abstract: A pressure sensor based on zinc oxide nanowires and a method of manufacturing a pressure sensor based on zinc oxide nanowires are provided. The manufacturing method includes: manufacturing a bottom electrode on a substrate; manufacturing a seed layer on the bottom electrode; manufacturing a zinc oxide nanowire layer on the seed layer; manufacturing a support layer on the zinc oxide nanowire layer; and manufacturing a top electrode on the support layer.
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公开(公告)号：US12293781B2
公开(公告)日：2025-05-06
申请号：US18261716
申请日：2021-01-21
Inventor： Huai Lin , Guozhong Xing , Zuheng Wu , Long Liu , Di Wang , Cheng Lu , Peiwen Zhang , Changqing Xie , Ling Li , Ming Liu
IPC: G11C11/16
Abstract: The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.
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公开(公告)号：US20240005077A1
公开(公告)日：2024-01-04
申请号：US18250461
申请日：2020-10-30
Inventor： Nianduan Lu , Ling Li , Wenfeng Jiang , Di GENG , Jiawei Wang , Ming Liu
CPC classification number: G06F30/39 , G16C60/00 , H01L29/786
Abstract: A method of designing a thin film transistor device, including: calculating characteristic parameters of searched materials; screening the materials according to a characteristic parameter threshold to obtain first active layer materials; simulating the first active layer material as an active layer material in a thin film transistor device model to obtain a device characteristic of the thin film transistor device; screening the first active layer materials according to a device characteristic threshold to obtain second active layer materials; taking the second active layer material as the active layer material of the thin film transistor device to perform an experiment; and selecting another second active layer material to perform the experiment once again when an experiment result does not meet a preset requirement, and a design of the thin film transistor device is completed until the experiment result meets the preset requirement.
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Patent Agency Ranking
公开(公告)号：US11215652B2
公开(公告)日：2022-01-04
申请号：US16065582
申请日：2015-12-25
Inventor： Guangwei Xu , Zhiheng Han , Wei Wang , Congyan Lu , Lingfei Wang , Ling Li , Ming Liu
Abstract: A method for obtaining a contact resistance of a planar device includes: obtaining a contact resistance of a planar device by using a potential measurement method, in the measurement of the surface potential distribution, the planar device is in a state of current flowing, a certain voltage drop is formed at a junction area of the device; extracting the voltage drop measured through the Kelvin microscope by using a linear fitting method; and dividing the measured voltage drop by the current flowing through the device, thereby accurately calculating the magnitude of the contact resistance at the junction area of the planar device. With the present invention, the contact resistance of the planar device can be precisely measured, which is suitable for the contact resistance measurement experiments of devices such as thin film transistors and diodes. The invention has the advantages of reasonable theory, accurate result, simple and easy operation, and is favorable for optimizing the device performance and establishing a complete electrical model of the device.
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5.发明申请公开(公告)号：US20180366643A1
公开(公告)日：2018-12-20
申请号：US16064116
申请日：2016-08-12
Inventor： Nianduan Lu , Pengxiao Sun , Ling Li , Ming Iiu , Qi Liu , Hangbing Lv , Shibing Long
CPC classification number: H01L45/128 , G01N25/20 , G11C7/04 , G11C13/0002 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/00 , H01L45/04 , H01L45/1233 , H01L45/1293
Abstract: A method for evaluating the thermal effects of 3D RRAM arrays and reducing thermal crosstalk, including the following steps: Step 1: calculating the temperature distribution in the array through 3D Fourier heat conduction equation; Step 2, selecting a heat transfer mode; Step 3, selecting an appropriate array structure; Step 4, analyzing the effect of position of programming device in the array on the temperature; Step 5, analyzing the thermal crosstalk effect in the array; Step 6, evaluating thermal effects and thermal crosstalk; Step 7, changing the array structure or modify operating parameters based on the evaluation results to reduce the thermal crosstalk. According to the method of the present invention, the influence of the position of the device on the temperature is analyzed according to the heat transfer mode of the 3D RRAM array, the thermal effect and the thermal crosstalk are evaluated, and the appropriate array structure and operating parameters are selected according to the evaluation result, which effectively improves the thermal stability of the device.
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公开(公告)号：US10418549B2
公开(公告)日：2019-09-17
申请号：US16064116
申请日：2016-08-12
Inventor： Nianduan Lu , Pengxiao Sun , Ling Li , Ming Liu , Qi Liu , Hangbing Lv , Shibing Long
Abstract: A method for evaluating the thermal effects of 3D RRAM arrays and reducing thermal crosstalk, including the following steps: Step 1: calculating the temperature distribution in the array through 3D Fourier heat conduction equation; Step 2, selecting a heat transfer mode; Step 3, selecting an appropriate array structure; Step 4, analyzing the effect of position of programming device in the array on the temperature; Step 5, analyzing the thermal crosstalk effect in the array; Step 6, evaluating thermal effects and thermal crosstalk; Step 7, changing the array structure or modify operating parameters based on the evaluation results to reduce the thermal crosstalk. According to the method of the present invention, the influence of the position of the device on the temperature is analyzed according to the heat transfer mode of the 3D RRAM array, the thermal effect and the thermal crosstalk are evaluated, and the appropriate array structure and operating parameters are selected according to the evaluation result, which effectively improves the thermal stability of the device.
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7.发明公开公开(公告)号：US20230263070A1
公开(公告)日：2023-08-17
申请号：US18003913
申请日：2020-12-31
Inventor： Guozhong Xing , Di Wang , Huai Lin , Long Liu , Yu Liu , Hangbing Lv , Changqing Xie , Ling Li , Ming Liu
CPC classification number: H10N50/10 , H10B61/22 , H10N50/85 , G11C11/161
Abstract: The present disclosure relates to a field of memory technical, and in particular to a magnetoresistive device, a method for changing a resistance state of the magnetoresistive device, and a synapse learning module. The magnetoresistive device includes a top electrode, a ferromagnetic reference layer, a tunneling layer, a ferromagnetic free layer, a spin-orbit coupling layer, and a bottom electrode that are arranged in sequence along a preset direction, where the spin-orbit coupling layer includes a first thickness region and a second thickness region distributed alternately, and a thickness of the first thickness region is different form a thickness of the second thickness region; and the ferromagnetic free layer includes a pinning region, and a position of the pinning region is in one-to-one correspondence with a position of the first thickness region.
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公开(公告)号：US11430385B2
公开(公告)日：2022-08-30
申请号：US17053992
申请日：2018-08-02
Inventor： Di Geng , Yue Su , Ling Li , Nianduan Lu , Ming Liu
IPC: G09G3/3233 , G09G3/3291
Abstract: A pixel compensation circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and an organic light-emitting diode, each of the first transistor to the sixth transistor including a drain, a source and a gate.
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