公开(公告)号：US20160268124A1

公开(公告)日：2016-09-15

申请号：US14821203

申请日：2015-08-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Xinyu Liu ,  Sen Huang ,  Xinhua Wang ,  Ke Wei ,  Wenwu Wang ,  Junfeng Li ,  Chao Zhao

IPC: H01L21/02 ,  H01L23/00

CPC classification number: H01L21/02271 ,  C23C16/0245 ,  C23C16/303 ,  H01L21/02164 ,  H01L21/02315 ,  H01L21/0254 ,  H01L21/02664

Abstract: A method for manufacturing a low interface state device includes performing a remote plasma surface process on a III-Nitride layer on a substrate; transferring the processed substrate to a deposition cavity via an oxygen-free transferring system; and depositing on the processed substrate in the deposition cavity. The deposition may be low pressure chemical vapor deposition (LPCVD). The interface state between a surface dielectric and III-Nitride material may be significantly decreased by integrating a low impairment remote plasma surface process and LPCVD.

Abstract translation: 低接口状态器件的制造方法包括在基板上的III-氮化物层上进行远程等离子体表面处理; 通过无氧转移系统将经处理的基底转移至沉积腔; 并沉积在沉积腔中的处理过的衬底上。 沉积可以是低压化学气相沉积（LPCVD）。 通过集成低损伤远程等离子体表面工艺和LPCVD，可以显着降低表面电介质和III-氮化物材料之间的界面状态。

公开(公告)号：US10276366B2

公开(公告)日：2019-04-30

申请号：US14821203

申请日：2015-08-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Xinyu Liu ,  Sen Huang ,  Xinhua Wang ,  Ke Wei ,  Wenwu Wang ,  Junfeng Li ,  Chao Zhao

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/30

Abstract: A method for manufacturing a low interface state device includes performing a remote plasma surface process on a III-Nitride layer on a substrate; transferring the processed substrate to a deposition cavity via an oxygen-free transferring system; and depositing on the processed substrate in the deposition cavity. The deposition may be low pressure chemical vapor deposition (LPCVD). The interface state between a surface dielectric and III-Nitride material may be significantly decreased by integrating a low impairment remote plasma surface process and LPCVD.

公开(公告)号：US11289594B2

公开(公告)日：2022-03-29

申请号：US16635323

申请日：2019-03-14

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Sen Huang ,  Xinhua Wang ,  Xinyu Liu ,  Yuankun Wang ,  Haibo Yin ,  Ke Wei

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: A GaN-based superjunction vertical power transistor and a manufacturing method thereof. The transistor includes: a N−-GaN layer; a first P-GaN layer as a current blocking layer, formed on the N−-GaN layer and having a gate region window; and a thin barrier Al(In, Ga)N/GaN heterostructure conformally formed on the current blocking layer and filling the bottom and one or more sidewalls of the gate region window, wherein the N−-GaN layer has an etched groove completely or partially filled with a second P-type GaN layer, an N+-GaN layer is formed under the second P-type GaN layer, and the N+-GaN layer is in direct contact with the second P-type GaN layer and the N−-GaN layer to form a superjunction composite structure.

公开(公告)号：US10749021B2

公开(公告)日：2020-08-18

申请号：US15333674

申请日：2016-10-25

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Sen Huang ,  Xinyu Liu ,  Xinhua Wang ,  Ke Wei

IPC: H01L29/778 ,  H01L21/02 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/47 ,  H01L29/66

Abstract: A GaN-based enhancement-mode power electronic device and a method for manufacturing the same. The GaN-based enhancement-mode power electronic device comprises: a substrate; a thin barrier Al(In,Ga)N/GaN heterostructure formed on the substrate; a gate, a source, and a drain formed on the thin barrier Al(In,Ga)N/GaN heterostructure. An AlN or SiNx passivation layer is formed on access regions between the gate and the source and between the gate and the drain, respectively, such that two dimensional electron gas is recovered in channels of the thin barrier Al(In,Ga)N/GaN heterostructure below the MN passivation layer by utilizing the MN passivation layer having polarization characteristics, or by using the SiNx passivation layer with positive fixed bulk/interface charges, so as to reduce on-resistance of the device and inhibit high-voltage current collapse in the device.

公开(公告)号：US10062775B2

公开(公告)日：2018-08-28

申请号：US15368098

申请日：2016-12-02

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Sen Huang ,  Xinyu Liu ,  Xinhua Wang ,  Ke Wei ,  Qilong Bao ,  Wenwu Wang ,  Chao Zhao

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L29/15 ,  H01L21/306

CPC classification number: H01L29/7786 ,  H01L21/30621 ,  H01L29/1066 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/432 ,  H01L29/66462

Abstract: A GaN-based power electronic device and a method for manufacturing the same is provided. The GaN-based power electronic device comprising a substrate and an epitaxial layer over the substrate. The epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer. The superlattice structure layer is provided over the heterostructure layer, and the P-type cap layer is provided over the superlattice structure layer. By using this electronic device, gate voltage swing and safe gate voltage range of the GaN-based power electronic device manufactured on the basis of the P-type cap layer technique may be further extended, and dynamic characteristics of the device may be improved. Therefore, application process for the GaN-based power electronic device that is based on the P-type cap layer technique will be promoted.