中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.036 seconds)

    Semiconductor device and method for manufacturing the same
    3.
    发明授权
    Semiconductor device and method for manufacturing the same 有权

    公开(公告)号：US11024708B1

    公开(公告)日：2021-06-01

    申请号：US16824761

    申请日：2020-03-20

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Yongliang Li ,  Xiaohong Cheng ,  Qingzhu Zhang ,  Huaxiang Yin ,  Wenwu Wang

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

    Abstract: A semiconductor device, including: a silicon substrate; multiple fin structures, formed on the silicon substrate, where each extends along a first direction; a shallow trench insulator, located among the multiple fin structures; a gate stack, intersecting with the multiple fin structures and extending along a second direction, where first spacers are formed on two sidewalls in the first direction of the gate stack; source-or-drain regions, formed on the multiple fin structures, and located at two sides of the gate stack along the first direction; and a channel region, including a portion of the multiple fin structures located between the first spacers. and notch structures. A notch structure recessed inward is located between each of the multiple fin structures and the silicon substrate. The notch structure includes an isolator that isolates each of the multiple fin structures from the silicon substrate.

    Transistor having a gate with a variable work function and method for manufacturing the same
    4.
    发明授权
    Transistor having a gate with a variable work function and method for manufacturing the same 有权

    公开(公告)号：US10312345B2

    公开(公告)日：2019-06-04

    申请号：US15871690

    申请日：2018-01-15

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Jinjuan Xiang ,  Xiaolei Wang ,  Hong Yang ,  Shi Liu ,  Junfeng Li ,  Wenwu Wang ,  Chao Zhao

    IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/265 ,  H01L29/49

    Abstract: The present disclosure provides a method for manufacturing a transistor having a gate with a variable work function, comprising: providing a semiconductor substrate; forming a dummy gate stack on the semiconductor substrate and performing ion implantation on an exposed area of the semiconductor substrate at both sides of the dummy gate stack to form source/drain regions; removing the dummy gate and annealing the source/drain regions; providing an atomic layer deposition reaction device; introducing a precursor source reactant into the atomic layer deposition reaction device; and controlling an environmental factor for the atomic layer deposition device to grow a work function metal layer. The present disclosure also provides a transistor having a gate with a variable work function. The present disclosure may adjust a variable work function, and may use the same material system to obtain an adjustable threshold voltage within an adjustable range.

    Low Interface State Device and Method for Manufacturing the Same
    5.
    发明申请
    Low Interface State Device and Method for Manufacturing the Same 审中-公开
    低接口状态设备及其制造方法

    公开(公告)号：US20160268124A1

    公开(公告)日：2016-09-15

    申请号：US14821203

    申请日：2015-08-07

    Applicant: Institute of Microelectronics, Chinese Academy of Sciences

    Inventor： Xinyu Liu ,  Sen Huang ,  Xinhua Wang ,  Ke Wei ,  Wenwu Wang ,  Junfeng Li ,  Chao Zhao

    IPC: H01L21/02 ,  H01L23/00

    CPC classification number: H01L21/02271 ,  C23C16/0245 ,  C23C16/303 ,  H01L21/02164 ,  H01L21/02315 ,  H01L21/0254 ,  H01L21/02664

    Abstract: A method for manufacturing a low interface state device includes performing a remote plasma surface process on a III-Nitride layer on a substrate; transferring the processed substrate to a deposition cavity via an oxygen-free transferring system; and depositing on the processed substrate in the deposition cavity. The deposition may be low pressure chemical vapor deposition (LPCVD). The interface state between a surface dielectric and III-Nitride material may be significantly decreased by integrating a low impairment remote plasma surface process and LPCVD.

    Abstract translation: 低接口状态器件的制造方法包括在基板上的III-氮化物层上进行远程等离子体表面处理; 通过无氧转移系统将经处理的基底转移至沉积腔; 并沉积在沉积腔中的处理过的衬底上。 沉积可以是低压化学气相沉积（LPCVD）。 通过集成低损伤远程等离子体表面工艺和LPCVD，可以显着降低表面电介质和III-氮化物材料之间的界面状态。

    Stacked nanowire or nanosheet gate-all-around device and method for manufacturing the same
    7.
    发明授权
    Stacked nanowire or nanosheet gate-all-around device and method for manufacturing the same 有权

    公开(公告)号：US11476328B2

    公开(公告)日：2022-10-18

    申请号：US16824810

    申请日：2020-03-20

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Yongliang Li ,  Xiaohong Cheng ,  Qingzhu Zhang ,  Huaxiang Yin ,  Wenwu Wang

    IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84

    Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.

    METHOD FOR INTEGRATING SURFACE-ELECTRODE ION TRAP AND SILICON PHOTOELECTRONIC DEVICE, INTEGRATED STRUCTURE, AND THREE-DIMENSIONAL STRUCTURE
    8.
    发明申请
    METHOD FOR INTEGRATING SURFACE-ELECTRODE ION TRAP AND SILICON PHOTOELECTRONIC DEVICE, INTEGRATED STRUCTURE, AND THREE-DIMENSIONAL STRUCTURE 有权

    公开(公告)号：US20210151613A1

    公开(公告)日：2021-05-20

    申请号：US17121396

    申请日：2020-12-14

    Applicant: Institute of Microelectronics, Chinese Academy of Sciences

    Inventor： Yan YANG ,  Zhihua Li ,  Wenwu Wang

    IPC: H01L31/0232 ,  H01L31/02

    Abstract: A method for integrating a surface-electrode ion trap and a silicon optoelectronic device, and an integrated structure. A silicon structure and a grating are formed on a wafer. A first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer are sequentially deposited above the wafer. An epitaxy opening is provided in the first dielectric layer to form single-photon avalanche detectors. First contacts vias connecting the detectors, and through silicon vias reaching a back surface of the wafer, are provided in the second dielectric layer and the third dielectric layer, respectively. Electrodes, the second contact vias and the third contact vias are provided in the fourth dielectric layer. The first contact vias are connected to a first electrode via the second contact vias, and the through silicon vias are connected to the first electrode and a second electrode via the third contact vias.

Patent Agency Ranking