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公开(公告)号：US12260902B2
公开(公告)日：2025-03-25
申请号：US18042574
申请日：2020-08-24
Inventor： Qing Luo , Bing Chen , Hangbing Lv , Ming Liu , Cheng Lu
IPC: G11C7/22 , G11C11/408 , G11C11/4094 , G11C11/4096 , H03K19/017
Abstract: A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.
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公开(公告)号：US12002500B2
公开(公告)日：2024-06-04
申请号：US17426053
申请日：2019-01-28
Inventor： Hangbing Lv , Qing Luo , Xiaoxin Xu , Tiancheng Gong , Ming Liu
CPC classification number: G11C11/2273 , G11C11/2275 , G11C11/2297 , G11C16/14 , G11C16/3404
Abstract: A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.
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公开(公告)号：US20210295143A1
公开(公告)日：2021-09-23
申请号：US17250569
申请日：2018-08-07
Inventor： Qi Liu , Xumeng Zhang , Ming Liu , Hangbing Lv , Shibing Long
Abstract: A neuron circuit (100), including a memristive element (M1), a trigger element (D1), a feedback element (T1) and an AND circuit (A1). The memristive element (M1) is used to receive an excitation signal. The trigger element (D1) is connected to the memristive element (M1) and is used to receive a clock control signal for the neuron circuit and an output signal of the memristive element (M1). The feedback element (T1) is connected to an output end of the trigger element (D1) and an input end of the memristive element (M1) and is used to control a voltage at the input end of the memristive element (M1). The AND circuit (A1) is used to perform an AND operation on an output signal of the trigger element (D1) and the clock control signal. An output signal of the AND circuit (A1) acts as an output signal of the neuron circuit (100).
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4.发明授权公开(公告)号：US09508776B2
公开(公告)日：2016-11-29
申请号：US14771145
申请日：2013-09-24
Inventor： Qi Liu , Ming Liu , Shibing Long , Hangbing Lv , Yan Wang
CPC classification number: H01L27/2463 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0073 , G11C2213/15 , H01L27/2409 , H01L45/04 , H01L45/08 , H01L45/124 , H01L45/1253 , H01L45/146 , H01L45/148
Abstract: A gating device cell for a cross array of bipolar resistive memory cells comprises an n-p diode and a p-n diode, wherein the n-p diode and the p-n diode have opposite polarities and are connected in parallel, such that the gating device cell exhibits a bidirectional rectification feature. The gating device cell exhibits the bidirectional rectification feature, that is, it can provide a relatively high current density at any voltage polarity in its ON state, and also a relatively great rectification ratio (Rv/2/RV) under a read voltage. Therefore, it is possible to suppress read crosstalk in the cross array of bipolar resistive memory cells to avoid misreading, thereby solving the problem that a conventional rectifier diode is only applicable to a cross array of unipolar resistive memory cells.
Abstract translation: 用于双极性电阻式存储单元的交叉阵列的门控器件单元包括np二极管和pn二极管，其中np二极管和pn二极管具有相反的极性并且并联连接，使得门控器件单元呈现双向整流特征 。 选通装置单元具有双向整流特征，即，其可以在其导通状态下的任何电压极性下提供相对高的电流密度，并且在读取电压下可以提供相对较大的整流比（Rv / 2 / RV）。 因此，可以抑制双极电阻存储单元的交叉阵列中的读串扰，以避免误读，从而解决了传统的整流二极管仅可应用于单极性电阻存储单元的交叉阵列的问题。
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5.发明公开公开(公告)号：US20230263070A1
公开(公告)日：2023-08-17
申请号：US18003913
申请日：2020-12-31
Inventor： Guozhong Xing , Di Wang , Huai Lin , Long Liu , Yu Liu , Hangbing Lv , Changqing Xie , Ling Li , Ming Liu
CPC classification number: H10N50/10 , H10B61/22 , H10N50/85 , G11C11/161
Abstract: The present disclosure relates to a field of memory technical, and in particular to a magnetoresistive device, a method for changing a resistance state of the magnetoresistive device, and a synapse learning module. The magnetoresistive device includes a top electrode, a ferromagnetic reference layer, a tunneling layer, a ferromagnetic free layer, a spin-orbit coupling layer, and a bottom electrode that are arranged in sequence along a preset direction, where the spin-orbit coupling layer includes a first thickness region and a second thickness region distributed alternately, and a thickness of the first thickness region is different form a thickness of the second thickness region; and the ferromagnetic free layer includes a pinning region, and a position of the pinning region is in one-to-one correspondence with a position of the first thickness region.
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Patent Agency Ranking
公开(公告)号：US11223013B2
公开(公告)日：2022-01-11
申请号：US16489266
申请日：2017-02-28
Inventor： Qi Liu , Xiaolong Zhao , Sen Liu , Ming Liu , Hangbing Lv , Shibing Long , Yan Wang , Facai Wu
IPC: H01L45/00
Abstract: The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.
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公开(公告)号：US11205750B2
公开(公告)日：2021-12-21
申请号：US16786346
申请日：2020-02-10
Inventor： Qing Luo , Hangbing Lv , Ming Liu , Xiaoxin Xu , Cheng Lu
Abstract: The present disclosure provides a 1S1R memory integrated structure and a method for fabricating the same, wherein the 1S1R memory integrated structure includes: a word line metal, a resistive material layer, a selector lower electrode, a selector material layer, a selector upper electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the selector upper electrode is formed in the groove. According to the 1S1R memory integrated structure and its fabricating method in the present disclosure, by the change of the integrated position of the selector, the device area of the selector is much larger than the device area of the memory, which significantly reduces the requirement for the on-state current density of the selector.
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公开(公告)号：US10665780B2
公开(公告)日：2020-05-26
申请号：US16085400
申请日：2016-03-18
Inventor： Ming Liu , Qing Luo , Xiaoxin Xu , Hangbing Lv , Shibing Long , Qi Liu
Abstract: A selector for a bipolar resistive random access memory and a method for fabricating the selector are provided. The method includes: providing a substrate; forming a lower electrode on the substrate, where the lower electrode is made of a metal, and the metal is made up of metal atoms which diffuse under an annealing condition of below 400° C.; forming a first metal oxide layer on the lower electrode; performing an annealing process on the first metal oxide layer to make the metal atoms in the lower electrode diffuse into the first metal oxide layer to form a first metal oxide layer doped with metal atoms; forming a second metal oxide layer on the first metal oxide layer doped with metal atoms; forming an upper electrode layer on the second metal oxide layer; and patterning the upper electrode layer to form an upper electrode.
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公开(公告)号：US12260911B2
公开(公告)日：2025-03-25
申请号：US18247213
申请日：2021-01-25
Inventor： Xiaoxin Xu , Jie Yu , Danian Dong , Zhaoan Yu , Hangbing Lv
IPC: G11C13/00
Abstract: The memory circuit structure includes: a storage array, wherein the storage array includes at least two storage units; a decoder connected with a bit line and a word line of the storage array respectively; a programming circuit configured to generate a voltage pulse or a constant current pulse; a polarity switching circuit connected with the programming circuit, and configured to implement a switching between a voltage programming and a current programming of the programming circuit under a set operation and a reset operation; a detection circuit connected with the storage array, and configured to detect a detection signal of a current or a voltage corresponding to the specific storage unit in the storage array and feed back the detection signal to a control unit, wherein the detection signal output by the detection circuit is configured to enable the polarity switching circuit to switch; and the control unit.
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公开(公告)号：US12205630B2
公开(公告)日：2025-01-21
申请号：US18005101
申请日：2020-08-24
Inventor： Qing Luo , Bing Chen , Hangbing Lv , Ming Liu , Cheng Lu
IPC: G11C11/4096 , G11C11/408 , G11C11/4094 , H03K19/017
Abstract: Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.
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