公开(公告)号：GB2307605A

公开(公告)日：1997-05-28

申请号：GB9621139

申请日：1996-10-10

Applicant: INT RECTIFIER CORP

Inventor： DUBHASHI AJIT ,  AFTANDILIAN LEON

IPC: H01L27/04 ,  H01L29/78 ,  H02M1/08 ,  H02M7/537 ,  H02M7/538 ,  H03B1/00 ,  H03F1/52 ,  H03K17/06 ,  H03K17/16

Abstract: In a level shifted high voltage MOSgate device driver which drives MOSgate devices such as IGBTs and power MOSFETs, effects of negative voltage swings caused by currents commutating through LS1 and LS2 inductances in the power circuits are avoided due to several measures. First, the values of the inductances LS1 and LS2 are reduced by keeping short conductor lengths, by other layout/wire bonding techniques to reduce the values of the LS1 and LS2 inductances. The external, charging capacitor Cb value is increased substantially to reduce the voltage buildup on the internal circuitry. A typical value is 0.47 mu F, for a given circuit, IGBT and layout combination. The size of the CVCC capacitor is selected to keep the supply voltage as stiff as possible. Preferably, CVCC is at about ten times the value of the sum of the Cb capacitance in the circuit. The resistance Rb in the bootstrap path is reduced as much as possible, preferably to zero. Finally, a resistor RCOM is optionally added between the common nodes of the driver circuit and the power device circuit.

公开(公告)号：ITMI962097A1

公开(公告)日：1998-04-10

申请号：ITMI962097

申请日：1996-10-10

Applicant: INT RECTIFIER CORP

Inventor： DUBHASHI AJIT ,  AFTANDILIAN LEON

IPC: H01L27/04 ,  H01L29/78 ,  H02M1/08 ,  H02M7/537 ,  H02M7/538 ,  H03B1/00 ,  H03F1/52 ,  H03K17/06 ,  H03K17/16

Abstract: In a level shifted high voltage MOSgate device driver which drives MOSgate devices such as IGBTs and power MOSFETs, effects of negative voltage swings caused by currents commutating through LS1 and LS2 inductances in the power circuits are avoided due to several measures. First, the values of the inductances LS1 and LS2 are reduced by keeping short conductor lengths, by other layout/wire bonding techniques to reduce the values of the LS1 and LS2 inductances. The external, charging capacitor Cb value is increased substantially to reduce the voltage buildup on the internal circuitry. A typical value is 0.47 mu F, for a given circuit, IGBT and layout combination. The size of the CVCC capacitor is selected to keep the supply voltage as stiff as possible. Preferably, CVCC is at about ten times the value of the sum of the Cb capacitance in the circuit. The resistance Rb in the bootstrap path is reduced as much as possible, preferably to zero. Finally, a resistor RCOM is optionally added between the common nodes of the driver circuit and the power device circuit.

公开(公告)号：SG72706A1

公开(公告)日：2000-05-23

申请号：SG1996010851

申请日：1996-10-10

Applicant: INT RECTIFIER CORP

Inventor： DUBHASHI AJIT ,  AFTANDILIAN LEON

IPC: H01L29/78 ,  H02M1/08 ,  H02M7/537 ,  H01L27/04 ,  H02M7/538 ,  H03B1/00 ,  H03F1/52 ,  H03K17/06 ,  H03K17/16 ,  H02M7/5387 ,  H03F3/42 ,  H03K17/64

Abstract: In a level shifted high voltage MOSgate device driver which drives MOSgate devices such as IGBTs and power MOSFETs, effects of negative voltage swings caused by currents commutating through LS1 and LS2 inductances in the power circuits are avoided due to several measures. First, the values of the inductances LS1 and LS2 are reduced by keeping short conductor lengths, by other layout/wire bonding techniques to reduce the values of the LS1 and LS2 inductances. The external, charging capacitor Cb value is increased substantially to reduce the voltage buildup on the internal circuitry. A typical value is 0.47 mu F, for a given circuit, IGBT and layout combination. The size of the CVCC capacitor is selected to keep the supply voltage as stiff as possible. Preferably, CVCC is at about ten times the value of the sum of the Cb capacitance in the circuit. The resistance Rb in the bootstrap path is reduced as much as possible, preferably to zero. Finally, a resistor RCOM is optionally added between the common nodes of the driver circuit and the power device circuit.

公开(公告)号：GB2307605B

公开(公告)日：2000-05-10

申请号：GB9621139

申请日：1996-10-10

Applicant: INT RECTIFIER CORP

Inventor： DUBHASHI AJIT ,  AFTANDILIAN LEON

IPC: H01L27/04 ,  H01L29/78 ,  H02M1/08 ,  H02M7/537 ,  H02M7/538 ,  H03B1/00 ,  H03F1/52 ,  H03K17/06 ,  H03K17/16

Abstract: In a level shifted high voltage MOSgate device driver which drives MOSgate devices such as IGBTs and power MOSFETs, effects of negative voltage swings caused by currents commutating through LS1 and LS2 inductances in the power circuits are avoided due to several measures. First, the values of the inductances LS1 and LS2 are reduced by keeping short conductor lengths, by other layout/wire bonding techniques to reduce the values of the LS1 and LS2 inductances. The external, charging capacitor Cb value is increased substantially to reduce the voltage buildup on the internal circuitry. A typical value is 0.47 mu F, for a given circuit, IGBT and layout combination. The size of the CVCC capacitor is selected to keep the supply voltage as stiff as possible. Preferably, CVCC is at about ten times the value of the sum of the Cb capacitance in the circuit. The resistance Rb in the bootstrap path is reduced as much as possible, preferably to zero. Finally, a resistor RCOM is optionally added between the common nodes of the driver circuit and the power device circuit.

公开(公告)号：IT1285497B1

公开(公告)日：1998-06-08

申请号：ITMI962097

申请日：1996-10-10

Applicant: INT RECTIFIER CORP

Inventor： DUBHASHI AJIT ,  AFTANDILIAN LEON

IPC: H01L27/04 ,  H01L29/78 ,  H02M1/08 ,  H02M7/537 ,  H02M7/538 ,  H03B1/00 ,  H03F1/52 ,  H03K17/06 ,  H03K17/16

Abstract: In a level shifted high voltage MOSgate device driver which drives MOSgate devices such as IGBTs and power MOSFETs, effects of negative voltage swings caused by currents commutating through LS1 and LS2 inductances in the power circuits are avoided due to several measures. First, the values of the inductances LS1 and LS2 are reduced by keeping short conductor lengths, by other layout/wire bonding techniques to reduce the values of the LS1 and LS2 inductances. The external, charging capacitor Cb value is increased substantially to reduce the voltage buildup on the internal circuitry. A typical value is 0.47 mu F, for a given circuit, IGBT and layout combination. The size of the CVCC capacitor is selected to keep the supply voltage as stiff as possible. Preferably, CVCC is at about ten times the value of the sum of the Cb capacitance in the circuit. The resistance Rb in the bootstrap path is reduced as much as possible, preferably to zero. Finally, a resistor RCOM is optionally added between the common nodes of the driver circuit and the power device circuit.

公开(公告)号：DE19641840A1

公开(公告)日：1997-06-05

申请号：DE19641840

申请日：1996-10-10

Applicant: INT RECTIFIER CORP

Inventor： DUBHASHI AJIT ,  AFTANDILIAN LEON

IPC: H01L27/04 ,  H01L29/78 ,  H02M1/08 ,  H02M7/537 ,  H02M7/538 ,  H03B1/00 ,  H03F1/52 ,  H03K17/06 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0944

Abstract: When commutation current begins to flow in the anti-parallel diode Dp in the lower part of a half-bridge, a negative voltage transient appears at the node Vo due to inductances Ls1 and Ls2, causing failure of the driver IC. These inductances are reduced by minimising conductor lengths and by other layout and wire bonding techniques. The bootstrap capacitor Cb and the power supply capacitor Cvcc are increased; Cvcc is preferably about ten times the sum of all the bootstrap capacitors in the circuit. The resistance Rb in the bootstrap charging circuit is minimised, and may be eliminated. Finally, a resistor Rcom may be added in the negative supply line 41 to reduce current flow in the substrate diode Ds. the driven devices may be IGBTs or power MOS transistors.

公开(公告)号：FR2739735A1

公开(公告)日：1997-04-11

申请号：FR9612391

申请日：1996-10-10

Applicant: INT RECTIFIER CORP

Inventor： DUBHASHI AJIT ,  AFTANDILIAN LEON

IPC: H01L27/04 ,  H01L29/78 ,  H02M1/08 ,  H02M7/537 ,  H02M7/538 ,  H03B1/00 ,  H03F1/52 ,  H03K17/06 ,  H03K17/16 ,  H02M1/12

Abstract: In a level shifted high voltage MOSgate device driver which drives MOSgate devices such as IGBTs and power MOSFETs, effects of negative voltage swings caused by currents commutating through LS1 and LS2 inductances in the power circuits are avoided due to several measures. First, the values of the inductances LS1 and LS2 are reduced by keeping short conductor lengths, by other layout/wire bonding techniques to reduce the values of the LS1 and LS2 inductances. The external, charging capacitor Cb value is increased substantially to reduce the voltage buildup on the internal circuitry. A typical value is 0.47 mu F, for a given circuit, IGBT and layout combination. The size of the CVCC capacitor is selected to keep the supply voltage as stiff as possible. Preferably, CVCC is at about ten times the value of the sum of the Cb capacitance in the circuit. The resistance Rb in the bootstrap path is reduced as much as possible, preferably to zero. Finally, a resistor RCOM is optionally added between the common nodes of the driver circuit and the power device circuit.