Abstract:
A method of operating a processor (12) including loading one or more bytes of data within a register associated with microengines (22 a-f) with a shifted value of an operand and preserving or cleaning the bytes of data that are not loaded. The method further includes providing a bit mask that specifies which of the one or more bytes of data within the register are affected.
Abstract:
A method of operating a processor comprises concatenating a first word and a second word to produce an intermediate result. An ALU (76a) shifts the intermediate result by a specified shift amount and stores, in a register (76b), the shifted intermediate result in a third word.
Abstract:
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write reference.
Abstract:
A processor such as a parallel hardware-based multithreaded processor (12) is described. The processor can execute a computer instruction that is a branch instruction that causes an execution stream to branch to an instruction at an address specified in the instruction if a state of a specified state name of the processor is a specified value.
Abstract:
A method of operating a processor (12) including receiving data in a processing thread having a processing thread number and shifting the data into a register corresponding to the processing thread number.
Abstract:
A method of operating a processor (12) including loading one or more bytes of data within a register associated with microengines (22 a-f) with a shifted value of an operand and preserving or cleaning the bytes of data that are not loaded. The method further includes providing a bit mask that specifies which of the one or more bytes of data within the register are affected.
Abstract:
Apparatus and methods for rack level pre-installed interconnect for enabling cableless server, storage, and networking deployment. Plastic cable waveguides are configured to couple millimeter-wave radio frequency (RF) signals between two or more Extremely High Frequency (EHF) transceiver chips, thus supporting millimeter-wave wireless communication links enabling components in the separate chassis to communicate without requiring wire or optical cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network/switch chassis. A plurality of plastic cable waveguide may be coupled to applicable support/mounting members, which in turn are mounted to a rack and/or top-of-rack switches. This enables the plastic cable waveguides to be pre-installed at the rack level, and further enables racks to be installed and replaced without requiring further cabling for the supported communication links. The communication links support link bandwidths of up to 6 gigabits per second, and may be aggregated to facilitate multi-lane links.
Abstract:
Apparatus and methods for cableless connection of components within chassis and between separate chassis. Pairs of Extremely High Frequency (EHF) transceiver chips supporting very short length millimeter-wave wireless communication links are configured to pass radio frequency signals through holes in one or more metal layers in separate chassis and/or frames, enabling components in the separate chassis to communicate without requiring cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network/switch chassis. The EHF-based wireless links support link bandwidths of up to 6 gigabits per second, and may be aggregated to facilitate multi-lane links.
Abstract:
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts (THREAD_3 ... THREAD_0). The processor maintains execution threads (THREAD_3 ... THREAD_0). The execution threads (THREAD_3 ... THREAD_0) access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread (THREAD_3 ... THREAD_0).
Abstract:
A controller for a random access memory has control logic, including an arbiter that detects a status of outstanding memory references. The controller selects a memory reference from one of a plurality queues of memory references. The control logic is responsive to a memory reference chaining bit that when set allows for special handling of contiguous memory references.