PARALLEL PROCESSOR ARCHITECTURE
    3.
    发明申请
    PARALLEL PROCESSOR ARCHITECTURE 审中-公开
    并行处理器架构

    公开(公告)号:WO0116782A9

    公开(公告)日:2002-06-27

    申请号:PCT/US0022322

    申请日:2000-08-15

    Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write reference.

    Abstract translation: 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。 处理器还包括存储器控制系统,该存储器控制系统具有第一存储器控制器,该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器,其基于存储器是否优化存储器引用 引用是读引用或写引用。

    CABLELESS CONNECTION APPARATUS AND METHOD FOR COMMUNICATION BETWEEN CHASSIS

    公开(公告)号:EP3127407A4

    公开(公告)日:2017-11-29

    申请号:EP15772334

    申请日:2015-03-11

    Applicant: INTEL CORP

    CPC classification number: H04L49/10 H04B1/40 H04L49/35 H04L67/10 H05K7/1492

    Abstract: Apparatus and methods for cableless connection of components within chassis and between separate chassis. Pairs of Extremely High Frequency (EHF) transceiver chips supporting very short length millimeter-wave wireless communication links are configured to pass radio frequency signals through holes in one or more metal layers in separate chassis and/or frames, enabling components in the separate chassis to communicate without requiring cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network/switch chassis. The EHF-based wireless links support link bandwidths of up to 6 gigabits per second, and may be aggregated to facilitate multi-lane links.

    DISTRIBUTED MEMORY CONTROL AND BANDWIDTH OPTIMIZATION
    10.
    发明申请
    DISTRIBUTED MEMORY CONTROL AND BANDWIDTH OPTIMIZATION 审中-公开
    分布式存储器控制和带宽优化

    公开(公告)号:WO0148619A3

    公开(公告)日:2002-11-14

    申请号:PCT/US0042663

    申请日:2000-12-06

    CPC classification number: G06F13/1642

    Abstract: A controller for a random access memory has control logic, including an arbiter that detects a status of outstanding memory references. The controller selects a memory reference from one of a plurality queues of memory references. The control logic is responsive to a memory reference chaining bit that when set allows for special handling of contiguous memory references.

    Abstract translation: 用于随机存取存储器的控制器具有控制逻辑,包括检测未完成存储器引用的状态的仲裁器。 控制器从存储器引用的多个队列中的一个队列中选择存储器引用。 控制逻辑响应于存储器参考链接位,当设置允许对连续存储器引用的特殊处理时。

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