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    METHOD AND APPARATUS FOR EFFICIENT PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC)
    3.
    发明申请
    METHOD AND APPARATUS FOR EFFICIENT PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) 审中-公开
    有效的可循环冗余检查（CRC）的方法和装置

    公开(公告)号：WO2009085489A3

    公开(公告)日：2009-08-27

    申请号：PCT/US2008084571

    申请日：2008-11-24

    Applicant: INTEL CORP ,  GOPAL VINDOH ,  OZTURK ERDINC ,  WOLRICH GILBERT ,  FEGHALI WAJDI

    Inventor： GOPAL VINDOH ,  OZTURK ERDINC ,  WOLRICH GILBERT ,  FEGHALI WAJDI

    IPC: G06F9/46 ,  G06F11/00 ,  G06F13/10

    CPC classification number: G06F7/724 ,  G06F7/72 ,  H03M13/09

    Abstract: A method and apparatus to optimize each of the plurality of reduction stages in a Cyclic Redundancy Check (CRC) circuit to produce a residue for a block of data decreases area used to perform the reduction while maintaining the same delay through the plurality of stages of the reduction logic. A hybrid mix of Karatsuba algorithm, classical multiplications and serial division in various stages in the CRC reduction circuit results in about a twenty percent reduction in area on the average with no decrease in critical path delay.

    Abstract translation: 一种用于优化循环冗余校验（CRC）电路中的多个还原级中的每一个以产生数据块的残余的方法和装置减少用于执行所述减少的区域，同时通过所述多个阶段保持相同的延迟 还原逻辑。 在CRC减少电路中，Karatsuba算法，经典乘法和串行划分的混合混合结果导致平均面积减少了约20％，而关键路径延迟没有减少。

    METHOD AND APPARATUS TO SUPPORT MULTIPLE MEMORY BANKS WITH A MEMORY BLOCK
    4.
    发明申请
    METHOD AND APPARATUS TO SUPPORT MULTIPLE MEMORY BANKS WITH A MEMORY BLOCK 审中-公开
    用存储块支持多个存储器的方法和装置

    公开(公告)号：WO2006069126A3

    公开(公告)日：2006-11-23

    申请号：PCT/US2005046297

    申请日：2005-12-20

    Applicant: INTEL CORP ,  JAIN SANJEEV ,  WOLRICH GILBERT ,  ROSENBLUTH MARK ,  BERNSTEIN DEBRA

    Inventor： JAIN SANJEEV ,  WOLRICH GILBERT ,  ROSENBLUTH MARK ,  BERNSTEIN DEBRA

    IPC: G06F13/16

    CPC classification number: G06F13/1673

    Abstract: A memory controller system includes a memory command storage module to store commands for a plurality of memory banks. The system includes a plurality of control mechanisms, each of which includes first and second pointers, to provide, in combination with a next field in each module location, a link list of commands for a given one of the plurality of memory banks.

    Abstract translation: 存储器控制器系统包括用于存储多个存储器组的命令的存储器命令存储模块。 该系统包括多个控制机制，每个控制机制包括第一和第二指针，以便与每个模块位置中的下一个区域组合提供多个存储体中给定的一个存储体的命令的链接列表。

    FREE LIST AND RING DATA STRUCTURE MANAGEMENT
    5.
    发明申请
    FREE LIST AND RING DATA STRUCTURE MANAGEMENT 审中-公开
    免费清单和环数据结构管理

    公开(公告)号：WO2004015525A3

    公开(公告)日：2005-10-20

    申请号：PCT/US0324345

    申请日：2003-08-04

    Applicant: INTEL CORP

    Inventor： WOLRICH GILBERT ,  SWEENEY JOHN ,  GUILFORD JAMES ,  ROSENBLUTH MARK ,  BERNSTEIN DEBRA

    IPC: G06F1/00 ,  H04L12/56

    CPC classification number: H04L49/9047 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031

    Abstract: A method of managing a free list and ring data structure, which may be used to store journaling information, by storing and modifying information describing a structure of the free list or ring data structure in a cache memory that may also be used to store information describing a structure of a queue of buffers.

    Abstract translation: 一种管理可用于存储日志信息的空闲列表和环形数据结构的方法，通过将描述自由列表或环形数据结构的结构的信息存储和修改，该高速缓冲存储器也可用于存储描述的信息 缓冲区队列的结构。

    DETERMINING A MESSAGE RESIDUE
    8.
    发明申请
    DETERMINING A MESSAGE RESIDUE 审中-公开
    确定消息剩余

    公开(公告)号：WO2009012050A2

    公开(公告)日：2009-01-22

    申请号：PCT/US2008068801

    申请日：2008-06-30

    Applicant: INTEL CORP ,  GUERON SHAY ,  GOPAL VINODH ,  FEGHALI WAJDI K ,  WOLRICH GILBERT

    Inventor： GUERON SHAY ,  GOPAL VINODH ,  FEGHALI WAJDI K ,  WOLRICH GILBERT

    IPC: G06F7/52

    CPC classification number: H03M13/091

    Abstract: A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments of the message. The technique also includes determining a modular remainder with respect to the polynomial for the message based on the set of modular remainders and a set of constants determined prior to accessing the message. The modular remainder with respect to the polynomial for the message is stored in a memory.

    Abstract translation: 确定消息余数的技术包括访问消息并同时针对消息的不同相应段针对多项式确定一组模块余数。 该技术还包括基于在访问消息之前确定的一组模块余数和一组常量来确定关于消息的多项式的模余数。 关于消息多项式的模余数存储在存储器中。

    METHOD AND APPARATUS FOR PERFORMING MODULAR EXPONENTIATIONS
    9.
    发明申请
    METHOD AND APPARATUS FOR PERFORMING MODULAR EXPONENTIATIONS 审中-公开
    执行模块化证据的方法和装置

    公开(公告)号：WO2006039068A3

    公开(公告)日：2006-06-22

    申请号：PCT/US2005031672

    申请日：2005-09-02

    Applicant: INTEL CORP ,  KOSHY KAMAL ,  WOLRICH GILBERT ,  SYDIR JAROSLAW ,  FEGHALI WAJDI

    Inventor： KOSHY KAMAL ,  WOLRICH GILBERT ,  SYDIR JAROSLAW ,  FEGHALI WAJDI

    IPC: G06F7/72

    CPC classification number: G06F7/728

    Abstract: An arrangement is provided for performing modular exponentiations. A modular exponentiation may be performed by using multiple Montgomery multiplications. A Montgomery multiplication comprises a plurality of iterations of basic operations (e.g., carry-save additions), and is performed by a Montgomery multiplication engine (MME). Multiple MMEs of smaller sizes may be chained together to perform modular exponentiations of larger sizes. Additionally, a single MME of a smaller size may be scheduled to perform modular exponentiations of larger sizes. Moreover, the process of performing a Montgomery multiplication may be pipelined both horizontally and vertically. Furthermore, processes of performing two Montgomery multiplications may be interleaved and performed by the same MME or chained MMEs.

    Abstract translation: 提供了一种用于执行模数乘方的布置。 可以通过使用多个蒙哥马利乘法来执行模幂运算。 蒙哥马利乘法包括多个基本操作的迭代（例如，进位保存添加），并且由蒙哥马利乘法引擎（MME）执行。 较小尺寸的多个MME可以链接在一起以执行较大尺寸的模数乘方。 此外，可以调度较小尺寸的单个MME来执行较大尺寸的模数乘方。 此外，执行蒙哥马利乘法的过程可以水平和垂直流水线。 此外，执行两个蒙哥马利乘法的处理可以由相同的MME或链接的MME进行交织和执行。

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