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    Identification device for identifying microprocessor, and method of identifying microprocessor
    1.
    发明专利
    Identification device for identifying microprocessor, and method of identifying microprocessor 有权
    识别微处理器的识别装置及识别微处理器的方法

    公开(公告)号：JP2006053943A

    公开(公告)日：2006-02-23

    申请号：JP2005275267

    申请日：2005-09-22

    Applicant: Intel Corp ,  インテル・コーポレーション

    Inventor： DREYER ROBERT S ,  ALPERT DONALD B

    IPC: G06F9/445 ,  G06F15/78 ,  G06F1/00 ,  G06F9/30 ,  G06F11/00 ,  G06F21/00

    CPC classification number: G06F21/73 ,  G06F9/30003 ,  G06F9/328 ,  G06F9/44505 ,  G06F11/006 ,  G06F2207/7219

    Abstract: PROBLEM TO BE SOLVED: To provide an identification device and its method for identifying a microprocessor during operation. SOLUTION: The microprocessor 10 reads out microprocessor ID data from a read-only memory 31 storing the microprocessor ID data for identifying itself in response to identification command, and stores the same in registers 20, 22 which can be selectively read out by a programmer. When the microprocessor 10 is identified, an appropriate function for the specific microprocessor can be enabled, and a work around program can be installed. The implementation of ID command in the microprocessor not having the identification device is inhibited. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供在操作期间识别微处理器的识别装置及其方法。 解决方案：微处理器10响应于识别命令从存储用于识别自身的微处理器ID数据的只读存储器31读出微处理器ID数据，并将其存储在寄存器20,22中，寄存器20,22可以被选择性地读出 一个程序员 当微处理器10被识别时，可以启用针对特定微处理器的适当功能，并且可以安装有关程序的工作。 在不具有识别装置的微处理器中实施ID命令被禁止。 版权所有（C）2006，JPO＆NCIPI

    4.
    发明专利
    未知

    公开(公告)号：DE4301417A1

    公开(公告)日：1993-07-29

    申请号：DE4301417

    申请日：1993-01-20

    Applicant: INTEL CORP

    Inventor： GROCHOWSKI EDWARD T ,  SHOEMAKER KENNETH D ,  ZAIDI AHMAD ,  ALPERT DONALD B

    IPC: G06F9/28 ,  G06F9/30 ,  G06F9/38

    Abstract: A dual instruction decoder issues two instructions in parallel within a single clock cycle if there are no register dependencies between the instructions, and if both instructions fall within a predetermined subset of the complete instruction set. A first pipeline executes any instruction issued from the full instruction set, while a second pipeline only executes a predetermined subset of instructions determined by principles of locality. A register dependency checker determines whether the designation register of a first instruction is used during the execution of a second instruction in an instruction sequence. When both instructions are within the subset and there are no dependencies, the first and second instructions can be issued in parallel in the first and second pipelines.

    Interleaved cache for multiple accesses per clock in a microprocessor
    7.
    发明专利
    Interleaved cache for multiple accesses per clock in a microprocessor 未知

    公开(公告)号：GB2277181B

    公开(公告)日：1995-12-13

    申请号：GB9407321

    申请日：1992-12-22

    Applicant: INTEL CORP

    Inventor： ALPERT DONALD B ,  CHOUDHURY MUSTAFIZ R ,  MILLS JACK D

    IPC: G06F12/08 ,  G11C11/401

    Abstract: An interleaved cache is used for multiple data accesses per clock in a microprocessor. The cache includes a storage array having multiple banks of single-ported memory cells for storing data, a bank selector for selecting banks in the storage array simultaneously according to the multiple data accesses, and a datapath for transfering data between execution units in the microprocessor and the storage array. The cache of the present invention also includes contention logic for prioritizing the multiple data accesses when multiple data accesses are to be same bank.

    8.
    发明专利
    未知

    公开(公告)号：DE4329336A1

    公开(公告)日：1994-03-03

    申请号：DE4329336

    申请日：1993-08-31

    Applicant: INTEL CORP

    Inventor： DREYER ROBERT S ,  ALPERT DONALD B

    IPC: G06F15/78 ,  G06F1/00 ,  G06F9/30 ,  G06F9/445 ,  G06F11/00 ,  G06F21/00

    Abstract: A multi-level identification apparatus and method for providing at least two types of identification information, including a first type for identifying the origin of a microprocessor and the number of levels of identification information available, and a second type for identifying a family, a model, a stepping ID, and features of a microprocessor. The apparatus includes a first memory element for storing an indicia string that identifies the origin of the microprocessor. The apparatus also includes a second memory element for storing other microprocessor ID data including data fields for specifically identifying the microprocessor. The apparatus includes control logic for executing an ID instruction that reads the indicia string or the microprocessor ID data, dependent upon a preselected type. Whichever identification information is read, it is stored in one or more general purpose registers for selective reading by a programmer. The method is available at any time while the microprocessor is operating.

    Identifying a computer microprocessor.
    9.
    发明专利
    Identifying a computer microprocessor. 未知

    公开(公告)号：GB2270176A

    公开(公告)日：1994-03-02

    申请号：GB9317872

    申请日：1993-08-27

    Applicant: INTEL CORP

    Inventor： DREYER ROBERT S ,  ALPERT DONALD B

    IPC: G06F15/78 ,  G06F1/00 ,  G06F9/30 ,  G06F9/445 ,  G06F11/00 ,  G06F21/00

    Abstract: An apparatus and method for identifying a microprocessor uses a read-only memory for storing microprocessor ID data, and control logic for executing an ID instruction that transfers the microprocessor ID data from the read-only memory to a register that can be selectively read by a programmer. The identification apparatus and method also includes an ID flag indicating availability of the ID instruction in the microprocessor, and a test flag program for testing the ID flag to determine whether or not to execute the ID instruction.

    A microprocessor with an external command mode for diagnosis and debugging
    10.
    发明专利
    A microprocessor with an external command mode for diagnosis and debugging 未知

    公开(公告)号：GB2266606A

    公开(公告)日：1993-11-03

    申请号：GB9218391

    申请日：1992-08-28

    Applicant: INTEL CORP

    Inventor： DREYER ROBERT S ,  ALPERT DONALD B ,  MODI NIMISH H ,  TRIPP MIKE J

    IPC: G06F11/22 ,  G01R31/317 ,  G01R31/3185 ,  G06F9/318 ,  G06F9/38 ,  G06F11/267 ,  G06F11/36 ,  G06F11/30

    Abstract: A microprocessor can be operated in an external command mode or a conventional processor-driven mode. A multiplexer 18 selects which instruction path, external or processor driven, is actually supplied to the execution unit 20. Using the external command mode, the user can examine and modify registers, memory, and I/O space without otherwise affecting their contents and, because direct access is provided into the execution unit, there is no implicit updating that would otherwise affect the state of the processor and require saving to an alternate memory. A conventional test access port 12 for implementing the external mode is modified to include an instruction register 36, a data register 38, and control logic 40. Mode selection is carried out by an external pin 30, an external command, and a debug exception. For ascertaining if the circuit is in the external command mode, an acknowledge pin 86 is provided to indicate when the execution unit is ready to accept an instruction.

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