公开(公告)号：JPH10228419A

公开(公告)日：1998-08-25

申请号：JP35482697

申请日：1997-12-24

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  HAMMOND GARY N

IPC: G06F12/10

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for simplifying the introduction of conversion from a virtual address into a physical address to a conversion unit. SOLUTION: A device to be used for a computer system is generally provided in a state including a conversion unit, a default attribute storage area and a preloading unit. The conversion unit stores conversion for converting a virtual address into a physical address and each conversion includes an attribute field. A default conversion attribute storing area stores several default conversion attributes. The preloading unit is connected to the default conversion unit and the conversion unit. When a signal indicating that the conversion of a virtual address is not stored in the conversion unit is received from the conversion unit, the preloading unit transmits a suitable default conversion attribute to the conversion unit in response to the received signal.

公开(公告)号：EP1027654A4

公开(公告)日：2002-09-25

申请号：EP98906115

申请日：1998-02-04

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  HAMMOND GARY N

IPC: G06F12/10 ,  G06F12/06 ,  G06F12/08

CPC classification number: G06F12/1009 ,  G06F2212/652

Abstract: A method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area (315) and a page table walker. The page size storage area is used to store a number of page sizes selected for translating (305) a number of virtual addresses. The page table walker includes a selection unit (320) coupled to the page size storage area, as well as a page entry address generator (325) coupled to the selection unit. For each virtual address received by the selection unit, the selection unit positions a field in that virtual address based on the page size selected for translating that virtual address. In response to receiving the bits in the field identified for each of the virtual addresses, the page entry address generator (325) identifies an entry in a page table based on those bits.

公开(公告)号：GB2383873A

公开(公告)日：2003-07-09

申请号：GB0308426

申请日：2001-09-20

Applicant: INTEL CORP

Inventor： HAMMOND GARY N ,  SUBRAMANIYAM GANESH

IPC: G06F1/20 ,  G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F1/26

Abstract: According to one embodiment, a method is disclosed. The method includes determining whether the temperature of a central processing unit (CPU) exceeds a predetermined threshold. In addition, the method includes generating a first interrupt if the temperature of the CPU exceeds the predetermined threshold and transitioning from a first execution mode to a second execution mode.

公开(公告)号：GB2329735A

公开(公告)日：1999-03-31

申请号：GB9828360

申请日：1997-06-26

Applicant: INTEL CORP

Inventor： SHARANGPANI HARSHVARDHAN P ,  HAMMOND GARY N ,  MULDER HANS J ,  ARORA JUDGE K

IPC: G06F9/38 ,  G06F9/00 ,  G06F9/32

Abstract: A microprocessor for efficient processing of instructions in a program flow including a conditional program flow control instruction, such as a branch instruction. The conditional program flow control instruction targets a first code section to be processed if the condition is resolved to be met, and a second code section to be processed if the condition is resolved to be not met. A fetch unit (304) fetches instructions to be processed and branch prediction logic (336) coupled to the fetch unit (304) predicts the resolution of the condition. The branch prediction logic (336) of the invention also determines whether the resolution logic is likely to be predicted accurately, resolution of the condition is unlikely to be predicted accurately. Stream management logic (314) responsive to the branch prediction logic (336) directs speculative processing of instructions from both the first and second code sections prior to resolution of the condition if the resolution of the condition is unlikely to be predicted accurately Results of properly executed instructions are then committed to architectural state in program order. In this manner, the invention reduces penalty related to mispredictions.

公开(公告)号：AU3507697A

公开(公告)日：1998-01-21

申请号：AU3507697

申请日：1997-06-26

Applicant: INTEL CORP

Inventor： SHARANGPANI HARSHVARDHAN P ,  HAMMOND GARY N ,  MULDER HANS J ,  ARORA JUDGE K

IPC: G06F9/38 ,  G06F9/00

公开(公告)号：AU4775796A

公开(公告)日：1996-08-27

申请号：AU4775796

申请日：1996-02-05

Applicant: INTEL CORP

Inventor： HAMMOND GARY N ,  KAHN KEVIN C ,  ALPERT DONALD B

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/455 ,  G06F9/22

Abstract: A data processor is described. The data processor is capable of decoding and executing the first instruction of a first instruction set and the second instruction of a second instruction set wherein the first instruction and the second instruction originate from a single computer program. Alternatively, the data processor can also execute a first instruction of a first instruction set in a first instruction set mode, receive a first interruption indication in the first instruction set mode, service the first interruption indication in a second instruction set mode, return to the first instruction set mode, receive a second interruption indication in the first instruction set mode, and service the second interruption indication in the first instruction set mode.

公开(公告)号：DE4234194A1

公开(公告)日：1993-04-22

申请号：DE4234194

申请日：1992-10-10

Applicant: INTEL CORP

Inventor： HAMMOND GARY N ,  DUBEY PRADEEP

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/0875 ,  G06F12/10 ,  G06F12/1036 ,  G06F12/12

公开(公告)号：DE10084753T5

公开(公告)日：2004-04-29

申请号：DE10084753

申请日：2000-05-26

Applicant: INTEL CORP

Inventor： ZAHIR ACHMED R ,  CRAWFORD JOHN H ,  HAMMOND GARY N

IPC: G06F12/10

Abstract: The present invention is a method and apparatus to map virtual memory space. A region register file provides a region identifier for a virtual address in the virtual memory space. The virtual address includes a virtual region number and a virtual page number. A virtual page table look-up circuit is coupled to the region register file to generate a page table entry (PTE) virtual address from virtual address parameters. The virtual address parameters include the virtual address.

公开(公告)号：DE69724572T2

公开(公告)日：2004-04-08

申请号：DE69724572

申请日：1997-05-23

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  HAMMOND GARY N

IPC: G06F12/10

公开(公告)号：GB2368429A

公开(公告)日：2002-05-01

申请号：GB0200392

申请日：2000-05-26

Applicant: INTEL CORP

Inventor： ZAHIR ACHMED R ,  HAMMOND GARY N ,  CRAWFORD JOHN H

IPC: G06F12/10

Abstract: The present invention is a method and apparatus to map virtual memory space. A region register file provides a region identifier for a virtual address in the virtual memory space. The virtual address includes a virtual region number and a virtual page number. A virtual page table look-up circuit is coupled to the region register file to generate a page table entry (PTE) virtual address from virtual address parameters. The virtual address parameters include the virtual address.