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    Mechanism for handling failing load check instructions
    4.
    发明专利
    Mechanism for handling failing load check instructions 未知

    公开(公告)号：GB2375201A

    公开(公告)日：2002-11-06

    申请号：GB0215183

    申请日：2000-11-20

    Applicant: INTEL CORP

    Inventor： ARORA JUDGE K

    IPC: G06F9/38 ,  G06F11/07

    Abstract: A mechanism is provided for recovering from a failing load check instruction in a processor that implements advanced load instructions. An advanced load address table (ALAT) tracks status information for the advanced load instruction. The status information is read when an associated load check operation is processed, and an exception is triggered if the status information indicates data returned by the advanced load operation was modified by a subsequent store operation. The load check instruction is converted to a load operation, instructions are flushed from the processor's instruction execution pipeline, and the pipeline is resteered to the first instruction that follows the load check instruction.

    A processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction
    6.
    发明专利
    A processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction 未知

    公开(公告)号：GB2329735A

    公开(公告)日：1999-03-31

    申请号：GB9828360

    申请日：1997-06-26

    Applicant: INTEL CORP

    Inventor： SHARANGPANI HARSHVARDHAN P ,  HAMMOND GARY N ,  MULDER HANS J ,  ARORA JUDGE K

    IPC: G06F9/38 ,  G06F9/00 ,  G06F9/32

    Abstract: A microprocessor for efficient processing of instructions in a program flow including a conditional program flow control instruction, such as a branch instruction. The conditional program flow control instruction targets a first code section to be processed if the condition is resolved to be met, and a second code section to be processed if the condition is resolved to be not met. A fetch unit (304) fetches instructions to be processed and branch prediction logic (336) coupled to the fetch unit (304) predicts the resolution of the condition. The branch prediction logic (336) of the invention also determines whether the resolution logic is likely to be predicted accurately, resolution of the condition is unlikely to be predicted accurately. Stream management logic (314) responsive to the branch prediction logic (336) directs speculative processing of instructions from both the first and second code sections prior to resolution of the condition if the resolution of the condition is unlikely to be predicted accurately Results of properly executed instructions are then committed to architectural state in program order. In this manner, the invention reduces penalty related to mispredictions.

    Mechanism for handling failing load check instructions
    8.
    发明专利
    Mechanism for handling failing load check instructions 未知

    公开(公告)号：GB2375201B

    公开(公告)日：2004-08-25

    申请号：GB0215183

    申请日：2000-11-20

    Applicant: INTEL CORP

    Inventor： ARORA JUDGE K

    IPC: G06F9/38 ,  G06F11/07

    Abstract: A mechanism is provided for recovering from a failing load check instruction in a processor that implements advanced load instructions. An advanced load address table (ALAT) tracks status information for the advanced load instruction. The status information is read when an associated load check operation is processed, and an exception is triggered if the status information indicates data returned by the advanced load operation was modified by a subsequent store operation. The load check instruction is converted to a load operation, instructions are flushed from the processor's instruction execution pipeline, and the pipeline is resteered to the first instruction that follows the load check instruction.

    Mechanism for handling failing load check instructions.
    9.
    发明专利
    Mechanism for handling failing load check instructions. 未知

    公开(公告)号：HK1047991A1

    公开(公告)日：2003-03-14

    申请号：HK03100089

    申请日：2003-01-03

    Applicant: INTEL CORP

    Inventor： ARORA JUDGE K

    IPC: G06F9/38 ,  G06F

    Abstract: A mechanism is provided for recovering from a failing load check instruction in a processor that implements advanced load instructions. An advanced load address table (ALAT) tracks status information for the advanced load instruction. The status information is read when an associated load check operation is processed, and an exception is triggered if the status information indicates data returned by the advanced load operation was modified by a subsequent store operation. The load check instruction is converted to a load operation, instructions are flushed from the processor's instruction execution pipeline, and the pipeline is resteered to the first instruction that follows the load check instruction.

    10.
    发明专利
    未知

    公开(公告)号：DE10085333T1

    公开(公告)日：2002-11-21

    申请号：DE10085333

    申请日：2000-11-20

    Applicant: INTEL CORP

    Inventor： ARORA JUDGE K

    IPC: G06F9/38

    Abstract: A mechanism is provided for recovering from a failing load check instruction in a processor that implements advanced load instructions. An advanced load address table (ALAT) tracks status information for the advanced load instruction. The status information is read when an associated load check operation is processed, and an exception is triggered if the status information indicates data returned by the advanced load operation was modified by a subsequent store operation. The load check instruction is converted to a load operation, instructions are flushed from the processor's instruction execution pipeline, and the pipeline is resteered to the first instruction that follows the load check instruction.

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