公开(公告)号：WO03028099A3

公开(公告)日：2003-07-03

申请号：PCT/US0225312

申请日：2002-08-08

Applicant: INTEL CORP

Inventor： MCCORMICK CAROLYN ,  JESSEP REBECCA ,  DUNGAN JOHN ,  BOGGS DAVID ,  SATO DARYL

IPC: H01L23/498 ,  H05K1/11 ,  H05K3/34

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H05K1/113 ,  H05K1/114 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/10734 ,  H05K2203/1394 ,  H01L2224/05599

Abstract: An arrangement of pads with selective via in pad for mounting a semiconductor package on a substrate. In order to strengthen the soldered bonds, standard pads, which have a stronger bond, are used in locations of greatest stress and deflection. Vias in pad (VIP) are used at all other locations to improve routing advantages due to their smaller surface area.

Abstract translation: 具有选择性通孔的焊盘的布置用于将半导体封装安装在衬底上。 为了加强焊接的连接，标准垫的粘合力更强，可用于最大应力和偏转位置。 由于其较小的表面积，垫（VIP）中的通孔用于所有其他位置以改善布线优势。

公开(公告)号：AU2003243239A1

公开(公告)日：2003-12-31

申请号：AU2003243239

申请日：2003-05-16

Applicant: INTEL CORP

Inventor： DUNGAN JOHN ,  PAEK GARY ,  BOGGS DAVID ,  SATO DARYL

IPC: H05K1/11 ,  H05K3/46

Abstract: An electronic assembly is disclosed. The electronic assembly includes a lower portion and a first elongate trace formed on an upper surface of the lower portion. The trace is covered by an upper portion, and an opening formed through an upper surface of the upper portion extends to the trace to expose a portion of the trace. A second elongate trace is formed on the upper portion. A portion of the second elongate trace positioned in the opening formed through the upper surface of the upper portion contacts the first elongate trace through the opening to form an electrical interconnection between the first trace and the second trace.