公开(公告)号：AT392126T

公开(公告)日：2008-04-15

申请号：AT03705923

申请日：2003-01-23

Applicant: INTEL CORP

Inventor： SATO DARYL ,  BRIST GARY ,  LONG GARY

IPC: H05K1/02 ,  H05K3/46

Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.

公开(公告)号：WO03028099A3

公开(公告)日：2003-07-03

申请号：PCT/US0225312

申请日：2002-08-08

Applicant: INTEL CORP

Inventor： MCCORMICK CAROLYN ,  JESSEP REBECCA ,  DUNGAN JOHN ,  BOGGS DAVID ,  SATO DARYL

IPC: H01L23/498 ,  H05K1/11 ,  H05K3/34

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H05K1/113 ,  H05K1/114 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/10734 ,  H05K2203/1394 ,  H01L2224/05599

Abstract: An arrangement of pads with selective via in pad for mounting a semiconductor package on a substrate. In order to strengthen the soldered bonds, standard pads, which have a stronger bond, are used in locations of greatest stress and deflection. Vias in pad (VIP) are used at all other locations to improve routing advantages due to their smaller surface area.

Abstract translation: 具有选择性通孔的焊盘的布置用于将半导体封装安装在衬底上。 为了加强焊接的连接，标准垫的粘合力更强，可用于最大应力和偏转位置。 由于其较小的表面积，垫（VIP）中的通孔用于所有其他位置以改善布线优势。

公开(公告)号：WO03067943A2

公开(公告)日：2003-08-14

申请号：PCT/US0302360

申请日：2003-01-23

Applicant: INTEL CORP

Inventor： SATO DARYL ,  BRIST GARY ,  LONG GARY

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K1/0265 ,  H05K1/0206 ,  H05K1/0219 ,  H05K1/0221 ,  H05K3/005 ,  H05K3/4644 ,  H05K2201/09036 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09981 ,  H05K2203/0108 ,  H05K2203/1189 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes and one or more conductive trenches connecting to at least one of the plurality of metalized planes.

Abstract translation: 一种装置，其包括多个金属化平面，分离多个金属化平面的一个或多个电介质层和连接到多个金属化平面中的至少一个的一个或多个导电沟槽。

公开(公告)号：AU2003207694A8

公开(公告)日：2003-09-02

申请号：AU2003207694

申请日：2003-01-23

Applicant: INTEL CORP

Inventor： BRIST GARY ,  LONG GARY ,  SATO DARYL

IPC: H05K1/02 ,  H05K3/46

Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.

公开(公告)号：DE60320219D1

公开(公告)日：2008-05-21

申请号：DE60320219

申请日：2003-01-23

Applicant: INTEL CORP

Inventor： SATO DARYL ,  BRIST GARY ,  LONG GARY

IPC: H05K1/02 ,  H05K3/46

Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.

公开(公告)号：AU2003272412A1

公开(公告)日：2004-04-08

申请号：AU2003272412

申请日：2003-09-12

Applicant: INTEL CORP

Inventor： BRIST GARY ,  LONG GARY ,  SATO DARYL

IPC: H01L21/268 ,  H01L21/48 ,  H05K3/06 ,  B23K26/34 ,  H01L23/498 ,  H01L21/24 ,  C23C8/78 ,  C25D5/02 ,  H01R13/03 ,  B23K26/00 ,  H05K3/02 ,  H05K3/10

Abstract: Formation of a mixed-material composition through diffusion using photo-thermal energy. The diffusion may be used to create electrically conductive traces. The diffusion may take place between material layers on one of a package substrate, semiconductor substrate, substrate for a printed circuit board (PCB), or other multi-layered substrate. The photo-thermal energy may be supplied by various devices, for example a YAG laser device, CO 2 laser device, or other energy source.

公开(公告)号：DE60320219T2

公开(公告)日：2009-05-14

申请号：DE60320219

申请日：2003-01-23

Applicant: INTEL CORP

Inventor： SATO DARYL ,  BRIST GARY ,  LONG GARY

IPC: H05K1/02 ,  H05K3/46

Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.

公开(公告)号：MY131938A

公开(公告)日：2007-09-28

申请号：MYPI20022983

申请日：2002-08-09

Applicant: INTEL CORP

Inventor： MCCORMICK CAROLYN ,  JESSEP REBECCA ,  DUNGAN JOHN ,  BOGGS DAVID W ,  SATO DARYL

IPC: H01L23/498 ,  H05K1/11 ,  H05K3/34

Abstract: AN ARRANGEMENT OF PADS (14, 20, 22) WITH SELECTIVE VIA (24) IN PAD (14, 20, 22) FOR MOUNTING A SEMICONDUCTOR PACKAGE (12) ON A SUBSTRATE (18).IN ORDER TO STRENGTHEN THE SOLDERED BONDS, STANDARD PADS (14, 20, 22), WHICH HAVE A STRONGER BOND, ARE USED IN LOCATIONS OF GREATEST STRESS AND DEFLECTION. VIAS (24) IN PAD (VIP) ARE USED AT ALL OTHER LOCATIONS TO IMPROVE ROUTING ADVANTAGES DUE TO THEIR SMALLER SURFACE AREA.(FIG 3)

公开(公告)号：MY129382A

公开(公告)日：2007-03-30

申请号：MYPI20022939

申请日：2002-08-07

Applicant: INTEL CORP

Inventor： BOGGS DAVID W ,  JESSEP REBECCA ,  MCCORMICK CAROLYN ,  SATO DARYL ,  DUNGAN JOHN

IPC: B32B3/10 ,  H05K1/02 ,  H05K3/34

Abstract: A REGISTRATION COUPON (20) IS PROVIDED FOR A PRINTED CIRCUIT BOARD (10) OR OTHER SUBSTRATE.THE REGISTRATION COUPON (20) MAY BE USED TO DETERMINE A HOLE-TO-OUTER LAYER FEATURE REGISTRATION AND A SOLDER MASK REGISTRATION. THE REGISTRATION COUPON (20) MAY INCLUDE A REGISTRATION HOLE PROVIDED ON THE CIRCUIT BOARD (10), A METAL PAD AND AN ANTI-PAD (40) PROVIDED ON THE CIRCUIT BOARD (10) ABOUT THE REGISTRATION HOLE (30), AND A SOLDER MASK (70) COVERING THE METAL PAD.(FIG 2)

公开(公告)号：AU2003243239A1

公开(公告)日：2003-12-31

申请号：AU2003243239

申请日：2003-05-16

Applicant: INTEL CORP

Inventor： DUNGAN JOHN ,  PAEK GARY ,  BOGGS DAVID ,  SATO DARYL

IPC: H05K1/11 ,  H05K3/46

Abstract: An electronic assembly is disclosed. The electronic assembly includes a lower portion and a first elongate trace formed on an upper surface of the lower portion. The trace is covered by an upper portion, and an opening formed through an upper surface of the upper portion extends to the trace to expose a portion of the trace. A second elongate trace is formed on the upper portion. A portion of the second elongate trace positioned in the opening formed through the upper surface of the upper portion contacts the first elongate trace through the opening to form an electrical interconnection between the first trace and the second trace.