公开(公告)号：DE19914210A1

公开(公告)日：1999-10-07

申请号：DE19914210

申请日：1999-03-29

Applicant: INTEL CORP

Inventor： ROUSSEL PATRICE ,  HINTON GLENN J ,  THAKKAR SHREEKANT S ,  BOSWELL BRENT R ,  MENEZES KAROL F

IPC: G06F9/302 ,  G06F15/00

Abstract: A single macroinstruction is received, which specifies at least two logical registers. These registers each store first and second operands in packed data form with data elements in mutual correspondence. An operation specified from the individual macroinstructions, is executed on numbers of first and second mutually-corresponding data elements of the first and second operands, at different times, using the same circuit to produce independently, numbers of first and second resulting data elements. These are stored in a single logical register as third packed data operands. An Independent claim is included for the corresponding processor and system.

公开(公告)号：DE19914210B4

公开(公告)日：2006-01-05

申请号：DE19914210

申请日：1999-03-29

Applicant: INTEL CORP

Inventor： ROUSSEL PATRICE ,  HINTON GLENN J ,  THAKKAR SHREEKANT S ,  BOSWELL BRENT R ,  MENEZES KAROL F

IPC: G06F9/302 ,  G06F15/00

Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

公开(公告)号：US6425073B2

公开(公告)日：2002-07-23

申请号：US80528001

申请日：2001-03-13

Applicant: INTEL CORP

Inventor： ROUSSEL PATRICE ,  HINTON GLENN J ,  THAKKAR SHREEKANT S ,  BOSWELL BRENT R ,  MENEZES KAROL F

IPC: G06F9/302 ,  G06F15/00 ,  G06F9/00

CPC classification number: G06F9/30014 ,  G06F9/30036 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3875 ,  G06F9/3885

Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

Abstract translation: 公开了一种用于交错执行指令的方法和装置。 根据本发明的一个实施例，接收单个宏指令，其中单个宏指令指定至少两个逻辑寄存器，并且其中两个逻辑寄存器分别存储具有相应数据元素的第一和第二压缩数据操作数。 然后，使用相同电路，在来自所述第一和第二打包数据操作数的第一和第二多个相应数据元素上独立地执行由单个宏指令指定的操作，以独立地生成第一和第二多个结果数据元素 。 第一和第二多个结果数据元素作为第三打包数据操作数存储在单个逻辑寄存器中。