公开(公告)号：US6425073B2

公开(公告)日：2002-07-23

申请号：US80528001

申请日：2001-03-13

Applicant: INTEL CORP

Inventor： ROUSSEL PATRICE ,  HINTON GLENN J ,  THAKKAR SHREEKANT S ,  BOSWELL BRENT R ,  MENEZES KAROL F

IPC: G06F9/302 ,  G06F15/00 ,  G06F9/00

CPC classification number: G06F9/30014 ,  G06F9/30036 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3875 ,  G06F9/3885

Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

Abstract translation: 公开了一种用于交错执行指令的方法和装置。 根据本发明的一个实施例，接收单个宏指令，其中单个宏指令指定至少两个逻辑寄存器，并且其中两个逻辑寄存器分别存储具有相应数据元素的第一和第二压缩数据操作数。 然后，使用相同电路，在来自所述第一和第二打包数据操作数的第一和第二多个相应数据元素上独立地执行由单个宏指令指定的操作，以独立地生成第一和第二多个结果数据元素 。 第一和第二多个结果数据元素作为第三打包数据操作数存储在单个逻辑寄存器中。

公开(公告)号：WO2012087471A3

公开(公告)日：2013-01-10

申请号：PCT/US2011061466

申请日：2011-11-18

Applicant: INTEL CORP ,  DAHLEN ERIC J ,  HINTON GLENN J ,  RAMANUJAN RAJ K

Inventor： DAHLEN ERIC J ,  HINTON GLENN J ,  RAMANUJAN RAJ K

IPC: G06F12/00

CPC classification number: G06F3/0611 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/0766 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0868 ,  G06F12/0893 ,  G06F2212/1024 ,  G06F2212/313 ,  G06F2212/7203 ,  G06F2212/7208 ,  G06F2212/7209 ,  G06F2212/7211 ,  G11C14/009

Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes "near memory" comprising memory made of volatile memory, and "far memory" comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as "main memory" to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

Abstract translation: 本发明的实施例描述了包括两级存储器的系统主存储器，其包括系统盘级存储器的缓存子集。 该主存储器包括包含由易失性存储器构成的存储器的“近存储器”和包括比近存储器更大和更慢的易失性或非易失性存储器存储器的“远存储器”。 远端存储器被呈现为主机OS的“主存储器”，而近端存储器是对OS是透明的远存储器的高速缓存，因此与OS显示与现有技术的主存储器解决方案相同。 两级存储器的管理可以通过经由主机CPU执行的逻辑和模块的组合来完成。 近端存储器可以通过高带宽，低延迟的方式耦合到主机系统CPU，用于高效处理。 远端存储器可以通过低带宽，高延迟手段耦合到CPU。

公开(公告)号：EP2761464A4

公开(公告)日：2015-06-17

申请号：EP11873012

申请日：2011-09-30

Applicant: INTEL CORP

Inventor： RAMANUJAN RAJ K ,  AGARWAL RAJAT ,  HINTON GLENN J

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/06 ,  G06F12/08 ,  G06F13/14 ,  G11C7/10

CPC classification number: G06F12/0811 ,  G06F12/0246 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2212/205 ,  G06F2212/283 ,  G06F2212/6046 ,  G06F2212/621 ,  G06F2212/7201 ,  G11C7/1045 ,  G11C7/1072 ,  G11C13/0004 ,  G11C14/0045

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

Abstract translation: 一种系统和方法被描述为INTEGRA廷存储器和存储层次包括计算机系统内的非易失性存储器中的动物。在一个实施方式中，PCMS存储器器件被用作在层次中的一个动物，有时被称为“远存储器”。 更高的性能的存储器装置：诸如DRAM放置在远存储器的正面和用于屏蔽的一些远存储器的性能限制。 这些较高性能存储设备被称为“近存储器”。在一个实施例中，“近存储器”被配置为在不同的操作模式的，包括多个操作（但不限于）第一模式，其中邻近存储器 操作为存储器缓存远存储器，并且其中所述近存储器分配与远存储器的系统地址空间的第一地址范围被分配系统地址空间的第二地址范围内的第二模式中，worin第一范围和 第二范围表示整个系统的地址空间。

公开(公告)号：EP2761466A4

公开(公告)日：2015-06-03

申请号：EP11873218

申请日：2011-09-30

Applicant: INTEL CORP

Inventor： RAMANUJAN RAJ K ,  AGARWAL RAJAT ,  CHENG KAI ,  POLEPEDDI TAARINYA ,  RAAD CAMILLE C ,  ZIMMERMAN DAVID J ,  SWAMINATHAN MUTHUKUMAR P ,  ZIAKAS DIMITRIOS ,  KUMAR MOHAN J ,  COURY BASSAM N ,  HINTON GLENN J

IPC: G06F12/00 ,  G06F12/08 ,  G11C7/10

CPC classification number: G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/2024 ,  G06F2212/205 ,  G11C11/40615 ,  G11C14/009 ,  Y02B60/1225 ,  Y02D10/13

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：EP1198747A4

公开(公告)日：2005-03-16

申请号：EP99902317

申请日：1999-01-15

Applicant: INTEL CORP

Inventor： KRICK ROBERT F ,  HINTON GLENN J ,  UPTON MICHAEL D ,  SAGER DAVID J ,  LEE CHAN W

IPC: G06F9/32 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3808 ,  G06F9/3802 ,  G06F9/3836 ,  G06F12/0875

Abstract: A cache memory (10) is constituted with a data array (14) and control logic (26). The data array (14) includes a number of data lines, and the control logic (26) operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more basic blocks of instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.

公开(公告)号：EP2656225A4

公开(公告)日：2015-01-21

申请号：EP11851888

申请日：2011-11-18

Applicant: INTEL CORP

Inventor： DAHLEN ERIC J ,  HINTON GLENN J ,  RAMANUJAN RAJ K

IPC: G06F12/00 ,  G06F11/07 ,  G06F12/02 ,  G06F12/08 ,  G11C14/00

CPC classification number: G06F3/0611 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/0766 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0868 ,  G06F12/0893 ,  G06F2212/1024 ,  G06F2212/313 ,  G06F2212/7203 ,  G06F2212/7208 ,  G06F2212/7209 ,  G06F2212/7211 ,  G11C14/009

Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes "near memory" comprising memory made of volatile memory, and "far memory" comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as "main memory" to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

Abstract translation: 本发明的实施例描述了包括两级存储器的系统主存储器，其包括系统盘级存储器的缓存子集。 该主存储器包括包含由易失性存储器构成的存储器的“近存储器”和包括比近存储器更大和更慢的易失性或非易失性存储器存储器的“远存储器”。 远端存储器被呈现为主机OS的“主存储器”，而近端存储器是对OS是透明的远存储器的高速缓存，因此与OS显示与现有技术的主存储器解决方案相同。 两级存储器的管理可以通过经由主机CPU执行的逻辑和模块的组合来完成。 近端存储器可以通过高带宽，低延迟的方式耦合到主机系统CPU，用于高效处理。 远端存储器可以通过低带宽，高延迟手段耦合到CPU。

公开(公告)号：EP0783735A4

公开(公告)日：2004-10-20

申请号：EP95931580

申请日：1995-08-24

Applicant: INTEL CORP

Inventor： GLEW ANDREW F ,  HINTON GLENN J

IPC: G06F9/312 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/30043 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3857 ,  G06F12/0804 ,  G06F12/0888

Abstract: A memory-type value identifying the type of memory contained with a range of memory locations is explicitly stored within a microprocessor (200-216). Prior to processing a memory micro-instruction such as a load or store, the memory-type is determined (214-216) for the memory location identified by the memory micro-instruction. Once the memory-type is known the memory micro-instruction is processed (218-230) in accordance with any one of a number or processing protocols including write-through processing (220), write-back processing (222), write-protect processing (224), restricted-cacheability processing (226), uncacheable speculatable write-combining processing (230), or uncacheable processing (228). By providing memory-type information explicitly within the microprocessor the protocol by which the micro-instruction is processed may be efficiently tailored to the memory-type. In an exemplary embodiment, the microprocessor is an out-of-order microprocessor (200) capable of generating speculative memory microinstructions (202-204).

公开(公告)号：DE102010013389B4

公开(公告)日：2022-11-24

申请号：DE102010013389

申请日：2010-03-30

Applicant: INTEL CORP

Inventor： TRIKA SANJEEV N ,  HUFFMAN AMBER D ,  BOYD JAMES A ,  HADY FRANK T ,  HINTON GLENN J ,  JUENEMANN DALE J ,  PINTO OSCAR P ,  TETRICK SCOTT R ,  BARNES THOMAS J ,  BURRIDGE SCOTT E

IPC: G06F12/08 ,  G06F12/02 ,  G06F13/10

Abstract: System, umfassend:ein Speichermedium, um Daten zu speichern;einen NAND-Flash-Speicher, um die Daten des Speichermediums zu cachen, undeine Cache-Richtlinien-Engine, um die Daten des Speichermediums in/von dem NAND-Flash-Speicher basierend zumindest auf Eingangs-Ausgangs-(I/O)-Zugriffsinformationen der Daten auf Dateiebene zu cachen oder zu entfernen, wobei die Caching-Richtlinie auf Dateiebene beinhaltet, dass die mit einer Datei verbundenen gecachten Daten in einer Caching-Einheit markiert werden, um es anderen Dateien zu ermöglichen, die gecachten Daten zu referenzieren oder darauf hinzuweisen,wenn die Zugriffsinformationen anzeigen, dass die Datei kopiert wird.

公开(公告)号：GB2514222A

公开(公告)日：2014-11-19

申请号：GB201404232

申请日：2014-03-11

Applicant: INTEL CORP

Inventor： MUTHIAH BHARATH ,  RASH WILLIAM BILL ,  HINTON GLENN J ,  DIXON MARTIN G ,  HAHN SCOTT D ,  PAPWORTH DAVID B

IPC: G06F9/455 ,  G06F9/45

Abstract: A system comprises a server which includes a processor having a first instruction set, wherein the server translates binary code having a second instruction set into an executable binary having the first instruction set. The server then executes the binary to generate a frame of rendered output, and this is transmitted to and displayed on a client device. The frame may be encoded into a media format before transmission. The translation, rendering, encoding and delivery process may be governed by Quality of Service (QoS) criteria, such as resolution, location, type and decode capabilities of the client device. A processor of the client device may have the second instruction set, and may request an application from the server. The binary translation may occur within a virtual machine.

公开(公告)号：DE102014003690A1

公开(公告)日：2014-09-18

申请号：DE102014003690

申请日：2014-03-14

Applicant: INTEL CORP

Inventor： RASH WILLIAM C ,  TOLL BRET L ,  HAHN SCOTT D ,  HINTON GLENN J

IPC: G06F9/30 ,  G06F9/318

Abstract: Ein Prozessor enthält unter einem Aspekt Dekodierlogik zum Erhalten eines ersten Befehls und zum Bestimmen, dass der erste Befehl emuliert werden soll. Der Prozessor enthält auch emulationsmodusbewusste Nachdekodier-Befehlsprozessorlogik, die mit der Dekodierlogik gekoppelt ist. Die emulationsmodusbewusste Nachdekodier-Befehlsprozessorlogik soll ein oder mehrere Steuersignale verarbeiten, die aus einem Befehl dekodiert werden. Der Befehl ist einer aus einem Satz von einem oder mehreren Befehlen, die zum Emulieren des ersten Befehls verwendet werden. Die ein oder mehreren Steuersignale sollen durch die emulationsmodusbewusste Nachdekodier-Befehlsprozessorlogik anders verarbeitet werden, wenn ein Emulationsmodus vorliegt, als wenn kein Emulationsmodus vorliegt. Andere Vorrichtungen sind ebenfalls offenbart, ebenso wie Verfahren und Systeme.