公开(公告)号：JP2014112383A

公开(公告)日：2014-06-19

申请号：JP2013262672

申请日：2013-12-19

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： FRANCIS X MCKEEN ,  CARLOS V ROZAS ,  UDAY R SAVAGANKAR ,  SIMON P JOHNSON ,  VINCENT R SCARLATA ,  MICHAEL A GOLDSMITH ,  ERNIE BRICKELL ,  LI JIANGTAO ,  HOWARD C HERBERT ,  PRASHANT DEWAN ,  STEPHEN J TOLOPKA ,  NEIGER GILBERT ,  DAVID DURHAM ,  GARY GRAUNKE ,  BERNARD LINT ,  DON A VAN DYKE ,  JOSEPH CIHULA ,  STALINSELVARAJ JEYASINGH ,  STEPHEN R VAN DOREN ,  DION RODGERS ,  JOHN GARNEY ,  ASHER ALTMAN

IPC: G06F12/14 ,  G06F12/10 ,  G06F21/10 ,  G06F21/12

Abstract: PROBLEM TO BE SOLVED: To enable integrity of secure applications and their data to be achieved within a computer system.SOLUTION: In a microprocessor 100, each processor core 105, 110 includes logic 119 for implementing secure enclave techniques, to perform efficient resource allocation among a plurality of cores or processors, establishing one or more secure enclaves in which an application and data may be stored and executed.

Abstract translation: 要解决的问题：使安全应用及其数据在计算机系统内实现的完整性。解决方案：在微处理器100中，每个处理器核心105,110包括用于实现安全飞行技术的逻辑119，以便在 多个核心或处理器，建立其中可以存储和执行应用程序和数据的一个或多个安全空间。

公开(公告)号：JP2017084392A

公开(公告)日：2017-05-18

申请号：JP2016250111

申请日：2016-12-22

Applicant: インテル・コーポレーション ,  Intel Corp

Inventor： FRANCIS X MCKEEN ,  CARLOS V ROZAS ,  UDAY R SAVAGANKAR ,  SIMON P JOHNSON ,  VINCENT R SCARLATA ,  MICHAEL A GOLDSMITH ,  ERNIE BRICKELL ,  LI JIANGTAO ,  HOWARD C HERBERT ,  PRASHANT DEWAN ,  STEPHEN J TOLOPKA ,  NEIGER GILBERT ,  DAVID DURHAM ,  GARY GRAUNKE ,  BERNARD LINT ,  DON A VAN DYKE ,  JOSEPH CIHULA ,  STALINSELVARAJ JEYASINGH ,  STEPHEN R VAN DOREN ,  DION RODGERS ,  JOHN GARNEY ,  ASHER ALTMAN

IPC: G06F21/10 ,  G06F21/57

Abstract: 【課題】コンピュータシステム内でセキュアなアプリケーションおよびデータの整合性をとることを可能とするプロセッサを提供する。【解決手段】マイクロプロセッサ100において、各プロセッサコア105,110内にセキュアなエンクレーブ技術を実行するための論理119を含み、効率的に複数のコアまたはプロセッサ間のリソース割り当てを行い、アプリケーションおよびデータを格納および実行することのできる1以上のセキュアなエンクレーブを構築する。【選択図】図1

公开(公告)号：GB2550698A

公开(公告)日：2017-11-29

申请号：GB201709341

申请日：2009-12-22

Applicant: INTEL CORP

Inventor： FRANCIS X MCKEEN ,  CARLOS V ROZAS ,  UDAY R SAVAGANKAR ,  SIMON P JOHNSON ,  VINCENT R SCARLATA ,  MICHAEL A GOLDSMITH ,  ERNIE BRICKELL ,  JIANG TAO LI ,  HOWARD C HERBERT ,  PRASHANT DEWAN ,  STEPHEN J TOLOPKA ,  GILBERT NEIGER ,  DAVID M DURHAM ,  GARY L GRAUNKE ,  BERNARD J LINT ,  DON A VAN DYKE ,  JOSEPH CIHULA ,  STALINSELVARAJ JEYASINGH ,  STEPHEN R VAN DOREN ,  DION RODGERS ,  JOHN I GARNEY

IPC: G06F21/74 ,  G06F21/72

Abstract: An instruction of software outside of a secure enclave is decoded and the decoded instruction is executed to read bytes from an enclave page cache (EPC) page of an enclave. The enclave is marked as being a debug enclave. An address of the bytes to read from the debug enclave is preferably provided in our CX. A debug bit is preferably set in the EPC to indicate that the enclave is a debug enclave. The contents of the debug enclave are preferably encrypted. The debug enclave may allow access using commands EDBGRD (read) and EDBGWR (write).

公开(公告)号：GB2528796B8

公开(公告)日：2018-04-18

申请号：GB201515835

申请日：2015-04-01

Applicant: INTEL CORP

Inventor： CARLOS V ROZAS ,  ILYA ALEXANDROVICH ,  ITTAI ANATI ,  ALEX BERENZON ,  MICHAEL A GOLDSMITH ,  BARRY E HUNTLEY ,  SIMON P JOHNSON ,  REBEKAH M LESLIE-HURD ,  FRANCIS X MCKEEN ,  GILBERT NEIGER ,  RINAT RAPPOPORT ,  SCOTT DION RODGERS ,  UDAY R SAVAGAONKAR ,  VINCENT R SCARLATA ,  VEDVYAS SHANBHOGUE ,  WESLEY H SMITH ,  WILLIAM COLIN WOOD ,  ANTON IVANOV

IPC: G06F12/14 ,  G06F9/30 ,  G06F12/1027 ,  G06F21/62

公开(公告)号：GB2534037A

公开(公告)日：2016-07-13

申请号：GB201601398

申请日：2015-04-01

Applicant: INTEL CORP

Inventor： CARLOS V ROZAS ,  ILYA ALEXANDROVICH ,  ITTAI ANATI ,  MICHAEL A GOLDSMITH ,  SIMON P JOHNSON ,  BARRY E HUNTLEY ,  REBEKAH M LESLIE-HURD ,  FRANCIS X MCKEEN ,  GILBERT NEIGER ,  RINAT RAPPOPORT ,  SCOTT DION RODGERS ,  UDAY R SAVAGAONKAR ,  VINCENT R SCARLATA ,  VEDVYAS SHANBHOGUE ,  WESLEY H SMITH ,  WILLIAM COLIN WOOD ,  ANTON IVANOV ,  ALEX BERENZON

IPC: G06F12/0808 ,  G06F9/30 ,  G06F21/62

Abstract: A processor has a portion of a cache to cache data from a protected partition. An instruction (ETRACK) causes it to record the number of hardware threads accessing the data in the portion of the cache. This may be the threads, which are executing code in the protected partition. When any of the threads exits the protected partition, the number is decremented. A second instruction (EWB) may cause the data in the cache to be evicted and written back to main memory when the number reaches zero. A third instruction (EBLOCK) may prevent the creation of new address translation entries for the pages in the cache. The data may be encrypted, when written to main memory, and decrypted, when read from main memory.

公开(公告)号：GB2528796A8

公开(公告)日：2018-04-18

申请号：GB201515835

申请日：2015-04-01

Applicant: INTEL CORP

Inventor： CARLOS V ROZAS ,  ILYA ALEXANDROVICH ,  ITTAI ANATI ,  ALEX BERENZON ,  MICHAEL A GOLDSMITH ,  BARRY E HUNTLEY ,  SIMON P JOHNSON ,  REBEKAH M LESLIE-HURD ,  FRANCIS X MCKEEN ,  GILBERT NEIGER ,  RINAT RAPPOPORT ,  SCOTT DION RODGERS ,  UDAY R SAVAGAONKAR ,  VINCENT R SCARLATA ,  VEDVYAS SHANBHOGUE ,  WESLEY H SMITH ,  WILLIAM COLIN WOOD ,  ANTON IVANOV

IPC: G06F12/14 ,  G06F9/30 ,  G06F12/1027 ,  G06F21/62

Abstract: A processor has multiple hardware threads and an enclave page cache. The processor has a first instruction to prevent new address translations being created. This instruction takes the address of a page in a secure enclave as a as a parameter. It prevents new entries being made in a translation look-aside buffer for that page. The processor has a second instruction to record the threads accessing an enclave. This instruction specifies the enclave identifier as a parameter and records the number of hardware threads accessing the enclave. The number is decremented whenever a thread exits the enclave. The processor has a third instruction to evict a page from an enclave page cache. The instruction takes the page address to evict as a parameter. It writes the page back to memory if the number of threads accessing the enclave is zero.

公开(公告)号：GB2550698B

公开(公告)日：2018-04-11

申请号：GB201709341

申请日：2009-12-22

Applicant: INTEL CORP

Inventor： FRANCIS X MCKEEN ,  CARLOS V ROZAS ,  UDAY R SAVAGANKAR ,  SIMON P JOHNSON ,  VINCENT R SCARLATA ,  MICHAEL A GOLDSMITH ,  ERNIE BRICKELL ,  JIANG TAO LI ,  HOWARD C HERBERT ,  PRASHANT DEWAN ,  STEPHEN J TOLOPKA ,  GILBERT NEIGER ,  DAVID M DURHAM ,  GARY L GRAUNKE ,  BERNARD J LINT ,  DON A VAN DYKE ,  JOSEPH CIHULA ,  STALINSELVARAJ JEYASINGH ,  STEPHEN R VAN DOREN ,  DION RODGERS ,  JOHN I GARNEY

IPC: G06F21/74 ,  G06F21/72

公开(公告)号：GB2481563B

公开(公告)日：2017-07-19

申请号：GB201118724

申请日：2009-12-22

Applicant: INTEL CORP

Inventor： FRANCIS X MCKEEN ,  CARLOS V ROZAS ,  UDAY R SAVAGANKAR ,  SIMON P JOHNSON ,  VINCENT R SCARLATA ,  MICHAEL A GOLDSMITH ,  ERNIE BRICKELL ,  JIANG TAO LI ,  HOWARD C HERBERT ,  PRASHANT DEWAN ,  STEPHEN J TOLOPKA ,  GILBERT NEIGER ,  DAVID M DURHAM ,  GARY GRAUNKE ,  BERNARD J LINT ,  DON A VAN DYKE ,  JOSEPH CIHULA ,  STALINSELVARAJ JEYASINGH ,  STEPHEN R VAN DOREN ,  DION RODGERS ,  JOHN I GARNEY

IPC: G06F21/74 ,  G06F21/72

公开(公告)号：GB2518796B

公开(公告)日：2020-05-20

申请号：GB201501444

申请日：2013-06-13

Applicant: INTEL CORP

Inventor： SIDDHARTHA CHHABRA ,  UDAY R SAVAGAONKAR ,  DAVID M DURHAM ,  NIRANJAN L COORAY ,  MEN LONG ,  CARLOS V ROZAS ,  ALPA T NARENDRA TRIVEDI

IPC: G06F12/14 ,  G06F21/71

Abstract: A processor includes a memory encryption engine that provides replay and confidentiality protections to a memory region. The memory encryption engine performs low-overhead parallelized tree walks along a counter tree structure. The memory encryption engine upon receiving an incoming read request for the protected memory region, performs a dependency check operation to identify dependency between the incoming read request and an in-process request and to remove the dependency when the in-process request is a read request that is not currently suspended.

公开(公告)号：GB2534037B8

公开(公告)日：2018-04-18

申请号：GB201601398

申请日：2015-04-01

Applicant: INTEL CORP

Inventor： CARLOS V ROZAS ,  ILYA ALEXANDROVICH ,  ITTAI ANATI ,  MICHAEL A GOLDSMITH ,  SIMON P JOHNSON ,  BARRY E HUNTLEY ,  REBEKAH M LESLIE-HURD ,  FRANCIS X MCKEEN ,  GILBERT NEIGER ,  RINAT RAPPOPORT ,  SCOTT DION RODGERS ,  UDAY R SAVAGAONKAR ,  VINCENT R SCARLATA ,  VEDVYAS SHANBHOGUE ,  WESLEY H SMITH ,  WILLIAM COLIN WOOD ,  ANTON IVANOV ,  ALEX BERENZON

IPC: G06F12/0808 ,  G06F9/30 ,  G06F21/62