公开(公告)号：JP2019091430A

公开(公告)日：2019-06-13

申请号：JP2018190245

申请日：2018-10-05

Applicant: INTEL CORP

Inventor： DAVID M DURHAM ,  SIDDHARTHA CHHABRA ,  RAVI L SAHITA ,  BARRY E HUNTLEY ,  GILBERT NEIGER ,  GIDEON GERZON ,  BAIJU V PATEL

IPC: G06F21/53 ,  G06F9/455 ,  G06F21/60

Abstract: 【課題】ゲストコンシューマのデータをセキュアに処理するパブリッククラウド環境を提供する。【解決手段】各ゲストコンシューマのワークロードがクラウドサービスプロバイダ(CSP)のサーバメモリに、CSPのワークロード管理ソフトウェアに知られていないコンシューマ提供のキーを用いて暗号化され、サーバメモリの中の、CSPのワークロード管理ソフトウェアによって指定されたメモリ位置に読み込まれる。CSP指定のメモリ位置に基づいて、ゲストワークロードは、メモリオーナーシップテーブル(MOT)で指定されるメモリマッピング構造及び他の種類のコンシューマデータが読み込まれるべき期待ハードウェア物理アドレスを決定する。MOTは、その後、CSP指定のメモリマッピングが期待通りであることを確認するのに用いられる。メモリオーナーシップテーブルエントリも、CSPに知られていないコンシューマ提供のキーによって暗号化される。【選択図】図8

公开(公告)号：NL2029042A

公开(公告)日：2022-05-24

申请号：NL2029042

申请日：2021-08-25

Applicant: INTEL CORP

Inventor： ANAND K ENAMANDRAM ,  MAHESH NATU ,  ROBERT A BRANCH ,  SIDDHARTHA CHHABRA ,  HORMUZD KHOSRAVI ,  TIFFANY J KASANICKY ,  MANJULA PEDDIREDDY

IPC: H04L9/08 ,  G06F12/14

Abstract: Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SOC) includes at least one persistent range register to indicate a persistent range of memory, an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and output the address as the output address when the address is not within the persistent range, and an encryption engine circuit to generate a ciphertext based on the output address.

公开(公告)号：GB2518796B

公开(公告)日：2020-05-20

申请号：GB201501444

申请日：2013-06-13

Applicant: INTEL CORP

Inventor： SIDDHARTHA CHHABRA ,  UDAY R SAVAGAONKAR ,  DAVID M DURHAM ,  NIRANJAN L COORAY ,  MEN LONG ,  CARLOS V ROZAS ,  ALPA T NARENDRA TRIVEDI

IPC: G06F12/14 ,  G06F21/71

Abstract: A processor includes a memory encryption engine that provides replay and confidentiality protections to a memory region. The memory encryption engine performs low-overhead parallelized tree walks along a counter tree structure. The memory encryption engine upon receiving an incoming read request for the protected memory region, performs a dependency check operation to identify dependency between the incoming read request and an in-process request and to remove the dependency when the in-process request is a read request that is not currently suspended.

公开(公告)号：NL2029297B1

公开(公告)日：2022-09-16

申请号：NL2029297

申请日：2021-09-30

Applicant: INTEL CORP

Inventor： RAJESH POORNACHANDRAN ,  DAVID ZAGE ,  VEDVYAS SHANBHOGUE ,  DAVID PUFFER ,  RONALD SILVAS ,  ALEX NAYSHTUT ,  NED M SMITH ,  ARAVINDH ANANTARAMAN ,  JULIEN CARRENO ,  TOMER LEVY ,  VIDHYA KRISHNAN ,  ANKUR SHAH ,  OMER BEN-SHALOM ,  ADITYA NAVALE ,  XIAOYU RUAN ,  DAVID COWPERTHWAITE ,  SCOTT JANUS ,  SIDDHARTHA CHHABRA

IPC: G06F21/57 ,  G06F21/78 ,  G06F21/84

Abstract: Systems, apparatuses and methods may provide for encryption based technology. Data may be encrypted locally with a graphics processor with encryption engines. The graphics processor components may be verified with a root-of-trust and based on collection 5 of claims. The graphics processor may further be able to modify encrypted data from a non- pageable format to a pageable format. The graphics processor may further process data associated with a virtual machine based on a key that is known by the virtual machine and the graphics processor. 10

公开(公告)号：NL2029047B1

公开(公告)日：2022-07-27

申请号：NL2029047

申请日：2021-08-25

Applicant: INTEL CORP

Inventor： HORMUZD KHOSRAVI ,  BARRY E HUNTLEY ,  THOMAS TOLL ,  SIDDHARTHA CHHABRA ,  RAMYA JAYARAM MASTI ,  VINCENT VON BOKERN

IPC: G06F12/14

Abstract: Embodiments of apparatuses, methods, and systems for scalable multi-key memory encryption are disclosed. In an embodiment, an apparatus includes a core, an encryption unit, and key identification hardware. The core is to write data to and read data from memory regions, each to be identified by a corresponding address. The encryption unit to encrypt data to be written and decrypt data to be read. The key identification hardware is to use a portion of the corresponding address to look up a corresponding key identifier in a key information data structure. The corresponding key identifier is one multiple key identifiers. The corresponding key identifier is to identify which one of multiple encryption keys is to be used to encrypt and decrypt the data.

公开(公告)号：NL2029042B1

公开(公告)日：2022-09-16

申请号：NL2029042

申请日：2021-08-25

Applicant: INTEL CORP

Inventor： ANAND K ENAMANDRAM ,  MAHESH NATU ,  ROBERT A BRANCH ,  SIDDHARTHA CHHABRA ,  HORMUZD KHOSRAVI ,  TIFFANY J KASANICKY ,  MANJULA PEDDIREDDY

IPC: H04L9/08 ,  G06F12/14

Abstract: Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SOC) includes at least one persistent range register to indicate a persistent range of memory, an address 5 modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and output the address as the output address when the address is not 10 within the persistent range, and an encryption engine circuit to generate a ciphertext based on the output address. 15

公开(公告)号：GB2523039B

公开(公告)日：2020-10-21

申请号：GB201509611

申请日：2013-06-24

Applicant: INTEL CORP

Inventor： SIDDHARTHA CHHABRA ,  RESHMA LAL ,  JASON MARTIN ,  DANIEL NEMIROFF

IPC: G06F21/71 ,  G06F21/50 ,  G06F21/54

公开(公告)号：NL2029297A

公开(公告)日：2022-06-17

申请号：NL2029297

申请日：2021-09-30

Applicant: INTEL CORP

Inventor： RAJESH POORNACHANDRAN ,  DAVID ZAGE ,  DAVID PUFFER ,  RONALD SILVAS ,  ALEX NAYSHTUT ,  NED M SMITH ,  ARAVINDH ANANTARAMAN ,  JULIEN CARRENO ,  TOMER LEVY ,  VIDHYA KRISHNAN ,  ANKUR SHAH ,  OMER BEN-SHALOM ,  ADITYA NAVALE ,  XIAOYU RUAN ,  DAVID COWPERTHWAITE ,  SCOTT JANUS ,  SIDDHARTHA CHHABRA ,  VEDVYAS SHANBOGUE

IPC: G06F21/57 ,  G06F21/78 ,  G06F21/84

Abstract: Systems, apparatuses and methods may provide for encryption based technology. Data may be encrypted locally with a graphics processor with encryption engines. The graphics processor components may be verified with a root-of-trust and based on collection 5 of claims. The graphics processor may further be able to modify encrypted data from a non- pageable format to a pageable format. The graphics processor may further process data associated with a virtual machine based on a key that is known by the virtual machine and the graphics processor. 10

公开(公告)号：NL2029047A

公开(公告)日：2022-05-24

申请号：NL2029047

申请日：2021-08-25

Applicant: INTEL CORP

Inventor： HORMUZD KHOSRAVI ,  BARRY E HUNTLEY ,  THOMAS TOLL ,  SIDDHARTHA CHHABRA ,  RAMYA JAYARAM MASTI ,  VINCENT VON BOKERN

IPC: G06F12/14

Abstract: Embodiments of apparatuses, methods, and systems for scalable multi-key memory encryption are disclosed. In an embodiment, an apparatus includes a core, an encryption unit, and key identification hardware. The core is to write data to and read data from memory regions, each to be identified by a corresponding address. The encryption unit to encrypt data to be written and decrypt data to be read. The key identification hardware is to use a portion of the corresponding address to look up a corresponding key identifier in a key information data structure. The corresponding key identifier is one multiple key identifiers. The corresponding key identifier is to identify which one of multiple encryption keys is to be used to encrypt and decrypt the data.

公开(公告)号：BR102020019667A2

公开(公告)日：2021-06-29

申请号：BR102020019667

申请日：2020-09-26

Applicant: INTEL CORP

Inventor： BARRY HUNTLEY ,  HORMUZD KHOSRAVI ,  RAMYA JAYARAM MASTI ,  SIDDHARTHA CHHABRA ,  VEDVYAS SHANBHOGUE ,  VINCENT VON BOKERN

IPC: H04L9/08 ,  H04L9/30

Abstract: método e aparelho para criptografia de memória total multichave baseada em derivação de chave dinâmica. a presente invenção refere-se a criptografia de memória total multichave baseada em derivação de chave dinâmica. em um exemplo, um processador inclui um conjunto de circuitos criptográficos, armazenamento com múltiplas divisões de chave e múltiplas chaves de criptografia completas, um conjunto de circuitos de busca e de decodificação para buscar e decodificar uma instrução que especifica um código de operação, um endereço e um keyid, sendo que o código de operação solicita que o processador use o endereço para determinar se deve usar uma chave explícita, nesse caso, o keyid é usado para selecionar uma dentre as múltiplas chaves de criptografia completas para uso como uma chave criptográfica, e, de outro modo, o processador deve derivar dinamicamente a chave criptográfica usando o keyid para selecionar uma das múltiplas divisões de chave, e fornecer a divisão de chave e uma chave raiz a uma função de derivação de chave para derivar a chave criptográfica, que é usada pelo conjunto de circuitos de criptografia para realizar uma operação criptográfica em uma localização de memória endereçada.