公开(公告)号：JP2009277228A

公开(公告)日：2009-11-26

申请号：JP2009116525

申请日：2009-05-13

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： BAUM DAN ,  DANY RYBNIKOV ,  ROTEM EFRAIM ,  KOMER RONNY

IPC: G06F9/48

CPC classification number: G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/3419 ,  G06F11/3476 ,  G06F2201/86 ,  G06F2201/88 ,  Y02D10/126 ,  Y02D10/172

Abstract: PROBLEM TO BE SOLVED: To provide a method for recognizing efficiency of a processor (for example, CPU) to dynamically regulate performance.
SOLUTION: An apparatus has a counter 108, an efficiency determination module 110, and a management module 112. The counter 108 determines the number of event occurrences relating to a processor component (e.g., a processor core 102) waiting for a response from a device. The efficiency determination module 110 determines an efficiency metric based on the number of event occurrences. The management module 112 establishes one or more operating characteristics for the processor component corresponding to the efficiency metric.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于识别处理器（例如，CPU）的效率以动态地调节性能的方法。 解决方案：设备具有计数器108，效率确定模块110和管理模块112.计数器108确定与等待响应的处理器组件（例如，处理器核心102）相关的事件发生的次数 从设备。 效率确定模块110基于事件发生的次数确定效率度量。 管理模块112为对应于效率度量的处理器组件建立一个或多个操作特性。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：DE102009019824A1

公开(公告)日：2009-11-26

申请号：DE102009019824

申请日：2009-05-04

Applicant: INTEL CORP

Inventor： BAUM DAN ,  DANY RYBNIKOV ,  ROTEM EFRAIM ,  KOMER RONNY

IPC: G06F1/32

Abstract: Techniques are disclosed involving techniques that may dynamically adjust processor (e.g., CPU) performance. For instance, an apparatus includes a counter, an efficiency determination module, and a management module. The counter determines a number of event occurrences, wherein each of the event occurrences involves a processor component (e.g., a processor core) awaiting a response from a device. The efficiency determination module determines an efficiency metric based on the number of event occurrences. The management module establishes one or more operational characteristics for the processor component that correspond to the efficiency metric. Other embodiments are described and claimed.

公开(公告)号：GB2459968A

公开(公告)日：2009-11-18

申请号：GB0908132

申请日：2009-05-12

Applicant: INTEL CORP

Inventor： BAUM DAN ,  DANY RYBNIKOV ,  ROTEM EFRAIM ,  KOMER RONNY

IPC: G06F1/32 ,  G06F11/34

Abstract: Disclosed is an apparatus that may dynamically adjust processor CPU performance. The apparatus has a counter, an efficiency determination module, and a management module. The counter determines the number of time an event occurs, each occurrences is a processor component (e.g., a processor core) awaiting or waiting for a response from a device. The efficiency determination module determines an efficiency metric based on the number of event occurrences, in preset a time interval. The management module establishes one or more operational characteristics for the processor component that correspond to the efficiency metric. The component is a core of a multi-core processor and each core may have its own power control apparatus. The operational characteristics include the power state, the clock frequency and/or the supply voltage. The events may be memory and/or input/output communications. The apparatus may include a temperature sensor to provide the management module with temperature data, so that the module can determine the available headroom of the processor ie if the power of the processor can be increased without the processor overheating.

公开(公告)号：GB2459968B

公开(公告)日：2011-03-02

申请号：GB0908132

申请日：2009-05-12

Applicant: INTEL CORP

Inventor： BAUM DAN ,  DANY RYBNIKOV ,  ROTEM EFRAIM ,  KOMER RONNY

IPC: G06F1/32 ,  G06F11/34

Abstract: Techniques are disclosed involving techniques that may dynamically adjust processor (e.g., CPU) performance. For instance, an apparatus includes a counter, an efficiency determination module, and a management module. The counter determines a number of event occurrences, wherein each of the event occurrences involves a processor component (e.g., a processor core) awaiting a response from a device. The efficiency determination module determines an efficiency metric based on the number of event occurrences. The management module establishes one or more operational characteristics for the processor component that correspond to the efficiency metric. Other embodiments are described and claimed.