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    NOISE SUPPRESSION FOR OPEN BIT LINE DRAM ARCHITECTURES
    1.
    发明申请
    NOISE SUPPRESSION FOR OPEN BIT LINE DRAM ARCHITECTURES 审中-公开
    用于打开位线DRAM架构的噪声抑制

    公开(公告)号：WO0233706A3

    公开(公告)日：2003-04-17

    申请号：PCT/US0131159

    申请日：2001-10-03

    Applicant: INTEL CORP ,  LU SHIH-LIEN ,  SOMASEKHAR DINESH ,  DE VIVEK

    Inventor： LU SHIH-LIEN ,  SOMASEKHAR DINESH ,  DE VIVEK

    IPC: G11C20060101 ,  G11C7/02 ,  G11C11/4094 ,  G11C11/4097 ,  H01L20060101 ,  G11C7/12 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4099 ,  H01L27/108

    CPC classification number: G11C11/4097 ,  G11C7/02 ,  G11C11/4094

    Abstract: An open bit line dynamic random access memory (DRAM) architecture uses a multiple layer bit line configuration to reduce coupling between switching bit lines in the device. In one approach, each successive cell within a row of DRAM cells is coupled to a bit line segment that is on a different metallization layer than a previous cell in the row. Shielding members are also provided between adjacent bit lines on a common metallization layer to further reduce noise coupling. Functionality is also provided for reducing the effect of word line to bit line coupling in the DRAM device using dummy signal injection techniques. In this manner, common mode noise that could otherwise saturate one or more sense amplifiers within the DRAM device is reduced or eliminated before such saturation can take place. In one approach, dummy cells and reference cells are provided for use in performing the signal injection. The principles of the present invention are particularly well suited for use within embedded DRAM structures where low charge storage capacity within individual cells reduces the signal voltage levels that are achievable.

    Abstract translation: 开放式位线动态随机存取存储器（DRAM）架构使用多层位线配置来减少器件中的开关位线之间的耦合。 在一种方法中，DRAM单元行内的每个连续单元被耦合到位于与行中的先前单元格不同的金属化层上的位线段。 屏蔽构件也设置在公共金属化层上的相邻位线之间，以进一步减少噪声耦合。 还提供了功能，用于使用虚拟信号注入技术来减少DRAM设备中字线对位线耦合的影响。 以这种方式，在这种饱和可能发生之前，可以减少或消除在DRAM装置内可以饱和一个或多个感测放大器的共模噪声。 在一种方法中，提供虚拟单元和参考单元用于执行信号注入。 本发明的原理特别适合于在嵌入式DRAM结构中使用，其中各个单元内的低电荷存储容量降低可实现的信号电压电平。

    A METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION THROUGH DYNAMIC CONTROL OF SUPPLY VOLTAGE AND BODY BIAS
    2.
    发明申请
    A METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION THROUGH DYNAMIC CONTROL OF SUPPLY VOLTAGE AND BODY BIAS 审中-公开
    通过动态电压和体态偏移的动态控制降低功耗的方法和装置

    公开(公告)号：WO2004061633A3

    公开(公告)日：2005-04-14

    申请号：PCT/US0339133

    申请日：2003-12-10

    Applicant: INTEL CORP

    Inventor： TSCHANZ JAMES ,  YE YIBIN ,  WEI LIQIONG ,  DE VIVEK

    IPC: G06F1/32

    CPC classification number: G06F1/3296 ,  G06F1/3203 ,  H03K2217/0018 ,  Y02D10/126 ,  Y02D10/172

    Abstract: An approach for power reduction of an integrated circuit device. In response to detecting a change in an activity factor associated with an integrated circuit device from a first activity factor to a second activity factor, a supply voltage and a body bias associated with the integrated circuit device are adjusted based on the second activity factor to reduce power consumption. For one aspect, the supply voltage and body bias are adjusted to maintain a substantially constant operating frequency for the integrated circuit device.

    Abstract translation: 一种用于集成电路装置的功率降低的方法。 响应于检测到与集成电路器件相关联的活动因素从第一活动因素到第二活动因素的变化，基于第二活动因素来调整与集成电路设备相关联的电源电压和身体偏压以减少 能量消耗。 一方面，调整电源电压和体偏置以保持集成电路器件的基本恒定的工作频率。

    AN APPARATUS AND METHOD FOR MULTI-PHASE TRANSFORMERS
    4.
    发明申请
    AN APPARATUS AND METHOD FOR MULTI-PHASE TRANSFORMERS 审中-公开
    多相变压器的装置和方法

    公开(公告)号：WO2006039048A3

    公开(公告)日：2006-08-10

    申请号：PCT/US2005031311

    申请日：2005-09-01

    Applicant: INTEL CORP ,  SCHROM GERHARD ,  HAZUCHA PETER ,  GARDNER DONALD ,  DE VIVEK ,  KARNIK TANAY

    Inventor： SCHROM GERHARD ,  HAZUCHA PETER ,  GARDNER DONALD ,  DE VIVEK ,  KARNIK TANAY

    IPC: H01F37/00 ,  H02M3/158

    CPC classification number: H02M3/1584 ,  H01F27/38 ,  H01F27/42 ,  H01F37/00 ,  H01F2038/026

    Abstract: A method and apparatus for multi-phase transformers (200) are described. In one embodiment, a coupled inductor topology for the multi-phase transformers comprising N primary inductors (210-240). In one embodiment, each primary inductor is coupled to one of N input nodes (201-1, 201-2, 201-3, 201-4) and a common output node (205). The transformer further includes N-1 secondary inductors (222-242) coupled in series between one input node (201-1) and the common output node (250). In one embodiment, the N-1 secondary inductors (222-242) are arranged to couple energy from N-1 of the primary inductors (220-240) to provide a common node voltage (250) as an average of N input node voltages (201-1, 201-2, 201-3, 201-4), wherein N is an integer greater than two. Other embodiments are described and claimed.

    Abstract translation: 描述了一种用于多相变压器（200）的方法和装置。 在一个实施例中，用于多相变压器的耦合电感器拓扑结构包括N个初级电感器（210-240）。 在一个实施例中，每个初级电感器耦合到N个输入节点（201-1,201-2,201-3,201-4-4）和公共输出节点（205）中的一个。 变压器还包括串联耦合在一个输入节点（201-1）和公共输出节点（250）之间的N-1个次级电感器（222-242）。 在一个实施例中，N-1次级电感器（222-242）被布置成耦合来自主电感器（220-240）的N-1的能量，以提供作为N个输入节点电压的平均值的公共节点电压（250） （201-1,201-2,201-3,201-4），其中N是大于2的整数。 描述和要求保护其他实施例。

    STATIC RANDOM ACCESS MEMORY WITH SYMMETRIC LEAKAGE-COMPENSATED BIT LINE
    6.
    发明申请
    STATIC RANDOM ACCESS MEMORY WITH SYMMETRIC LEAKAGE-COMPENSATED BIT LINE 审中-公开
    具有对称泄漏补偿位线的静态随机存取存储器

    公开(公告)号：WO2004025661A2

    公开(公告)日：2004-03-25

    申请号：PCT/US0327789

    申请日：2003-09-05

    Applicant: INTEL CORP

    Inventor： ALVANDPOUR ATILA ,  SOMASEKHAR DINESH ,  HSU STEVEN ,  KRISHNAMURTY RAM ,  DE VIVEK

    IPC: G11C11/412 ,  G11C11/419

    CPC classification number: G11C11/412 ,  G11C11/419

    Abstract: An eight-cell memory cell for static random access memory, the memory cell comprising cross-coupled inverters to store the information bit, two access nMOSFETs connected to local bit lines to access the stored information bit, and two nMOSFETs each having a gate connected to ground and coupled to the local bit lines and the cross-coupled inverters so that sub-threshold leakage currents to and from the local bit lines for a memory cell not being read are balanced.

    Abstract translation: 一种用于静态随机存取存储器的八单元存储单元，该存储单元包括交叉耦合的反相器以存储信息位，连接到局部位线以访问存储的信息位的两个存取nMOSFET，以及两个nMOSFET，每个nMOSFET具有连接到 并且耦合到本地位线和交叉耦合的反相器，使得用于未被读取的存储单元的去往和来自局部位线的亚阈值泄漏电流被平衡。

    Sistema e método de implementação de uma matriz de dispositivo programável em um sistema eletrônico
    8.
    发明专利
    Sistema e método de implementação de uma matriz de dispositivo programável em um sistema eletrônico 未知

    公开(公告)号：BR112014024312B1

    公开(公告)日：2022-04-12

    申请号：BR112014024312

    申请日：2012-03-30

    Applicant: INTEL CORP

    Inventor： RAYCHOWDHURY ARIJIT ,  JAMES JIM TSCHANZ ,  DE VIVEK

    IPC: G11C11/16 ,  G11C16/06

    Abstract: elementos de memória baseados em torque de transferência de rotação para matrizes de dispositivos programáveis. a invenção refere-se a matrizes de dispositivo semicondutor, como matrizes de portas de campo programáveis (fpga), matrizes lógicas programáveis complexas (cpla), que usam elementos de memória baseados em um torque de transferência de rotação (stt). os elementos de memória baseados em stt podem ser usados em fpgas/cplas autônomas, ou podem ser combinados em microprocessadores e/ou sistema em chip (soc) de processamento de sinal digital (dsp) para promover flexibilidade de projeto para a implementação de uma arquitetura de hardware reconfigurável, segura, escalável e de baixo consumo. como a configuração é armazenada na matriz fpga/cpla, elimina-se a necessidade de carregar a configuração da memória externa toda vez que o dispositivo for ligado. além da inicialização instantânea, a eliminação do tráfego de configuração e/s resulta em economias de energia e na possível redução do número de pinos. ocorre grande melhoria da segurança, pela eliminação da necessidade de armazenar dados de configuração na memória externa.

    Dual threshold voltage sram cell with bit line leakage control
    10.
    发明专利
    Dual threshold voltage sram cell with bit line leakage control 未知

    公开(公告)号：HK1037778A1

    公开(公告)日：2002-02-15

    申请号：HK01108612

    申请日：2001-12-07

    Applicant: INTEL CORP

    Inventor： KESHAVARZI ALI ,  ZHANG KEVIN ,  YE YIBIN ,  DE VIVEK

    IPC: G11C20060101 ,  G11C11/412 ,  G11C11/418

    Abstract: In some embodiments, the invention includes an integrated circuit including a bitline and a bitline#, wordlines, and memory cells. The memory cells each corresponding to one of the wordlines and each include first and second pass transistors coupled between first and second storage nodes, respectively, and the bitline and bitline#, respectively, the corresponding wordline being coupled to gates of the first and second pass transistors. The memory cells include first and second inverters cross-coupled between the first and second storage nodes, wherein the first and second pass transistors each have a lower threshold voltage than do transistors of the first and second inverters. Wordline voltage control circuitry coupled to the wordlines selectively controls wordline signals on the wordlines. In some embodiments, the wordline voltage control circuitry asserts the wordline signal for a selected wordline corresponding to a memory cell selected to be read and underdrives the wordline signals for the wordlines not corresponding to the selected memory cell.

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