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    INTEGRATED CIRCUIT, 1T-1C EMBEDDED MEMORY CELL CONTAINING SAME, AND METHOD OF MANUFACTURING 1T-1C MEMORY CELL FOR EMBEDDED MEMORY APPLICATION
    2.
    发明申请
    INTEGRATED CIRCUIT, 1T-1C EMBEDDED MEMORY CELL CONTAINING SAME, AND METHOD OF MANUFACTURING 1T-1C MEMORY CELL FOR EMBEDDED MEMORY APPLICATION 审中-公开
    集成电路，1T-1C嵌入式存储器单元以及制造用于嵌入式存储器应用的1T-1C存储器单元的方法

    公开(公告)号：WO2010074948A2

    公开(公告)日：2010-07-01

    申请号：PCT/US2009067066

    申请日：2009-12-08

    Applicant: INTEL CORP ,  DOYLE BRIAN S ,  SOMASEKHAR DINESH ,  DEWEY GILBERT ,  SURI SATYARTH

    Inventor： DOYLE BRIAN S ,  SOMASEKHAR DINESH ,  DEWEY GILBERT ,  SURI SATYARTH

    IPC: H01L27/108 ,  H01L21/8242

    CPC classification number: H01L28/90 ,  H01L27/10894 ,  H01L27/10897

    Abstract: An integrated circuit includes a semiconducting substrate (110), electrically conductive layers (120) over the semiconducting substrate, and a capacitor (130) at least partially embedded within the semiconducting substrate such that the capacitor is entirely underneath the electrically conductive layers. A storage node voltage is on an outside layer (132) of the capacitor. In the same or another embodiment, the integrated circuit may act as a 1T-1C embedded memory cell including the semiconducting substrate, an electrically insulating stack (160) over the semiconducting substrate, a transistor (140) including a source/drain region (142) within the semiconducting substrate and a gate region (141) above the semiconducting substrate, a trench (111) extending through the electrically insulating layers and into the semiconducting substrate, a first electrically insulating layer (131) located within the trench, and the capacitor located within the trench interior to the first electrically insulating layer.

    Abstract translation: 集成电路包括半导体衬底（110），半导体衬底上的导电层（120）以及至少部分嵌入半导体衬底内的电容器（130），使得电容器完全位于导电层下方。 存储节点电压位于电容器的外层（132）上。 在相同或另一个实施例中，集成电路可以充当包括半导体衬底，半导体衬底之上的电绝缘堆栈（160），包括源极/漏极区域（142）的晶体管（140）的1T-1C嵌入式存储器单元 ）在半导体衬底和半导体衬底上方的栅极区域（141）之间;沟槽（111），延伸穿过电绝缘层并进入半导体衬底;位于沟槽内的第一电绝缘层（131）;以及电容器 位于第一电绝缘层内部的沟槽内。

    NOISE SUPPRESSION FOR OPEN BIT LINE DRAM ARCHITECTURES
    3.
    发明申请
    NOISE SUPPRESSION FOR OPEN BIT LINE DRAM ARCHITECTURES 审中-公开
    用于打开位线DRAM架构的噪声抑制

    公开(公告)号：WO0233706A3

    公开(公告)日：2003-04-17

    申请号：PCT/US0131159

    申请日：2001-10-03

    Applicant: INTEL CORP ,  LU SHIH-LIEN ,  SOMASEKHAR DINESH ,  DE VIVEK

    Inventor： LU SHIH-LIEN ,  SOMASEKHAR DINESH ,  DE VIVEK

    IPC: G11C20060101 ,  G11C7/02 ,  G11C11/4094 ,  G11C11/4097 ,  H01L20060101 ,  G11C7/12 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4099 ,  H01L27/108

    CPC classification number: G11C11/4097 ,  G11C7/02 ,  G11C11/4094

    Abstract: An open bit line dynamic random access memory (DRAM) architecture uses a multiple layer bit line configuration to reduce coupling between switching bit lines in the device. In one approach, each successive cell within a row of DRAM cells is coupled to a bit line segment that is on a different metallization layer than a previous cell in the row. Shielding members are also provided between adjacent bit lines on a common metallization layer to further reduce noise coupling. Functionality is also provided for reducing the effect of word line to bit line coupling in the DRAM device using dummy signal injection techniques. In this manner, common mode noise that could otherwise saturate one or more sense amplifiers within the DRAM device is reduced or eliminated before such saturation can take place. In one approach, dummy cells and reference cells are provided for use in performing the signal injection. The principles of the present invention are particularly well suited for use within embedded DRAM structures where low charge storage capacity within individual cells reduces the signal voltage levels that are achievable.

    Abstract translation: 开放式位线动态随机存取存储器（DRAM）架构使用多层位线配置来减少器件中的开关位线之间的耦合。 在一种方法中，DRAM单元行内的每个连续单元被耦合到位于与行中的先前单元格不同的金属化层上的位线段。 屏蔽构件也设置在公共金属化层上的相邻位线之间，以进一步减少噪声耦合。 还提供了功能，用于使用虚拟信号注入技术来减少DRAM设备中字线对位线耦合的影响。 以这种方式，在这种饱和可能发生之前，可以减少或消除在DRAM装置内可以饱和一个或多个感测放大器的共模噪声。 在一种方法中，提供虚拟单元和参考单元用于执行信号注入。 本发明的原理特别适合于在嵌入式DRAM结构中使用，其中各个单元内的低电荷存储容量降低可实现的信号电压电平。

    STATIC RANDOM ACCESS MEMORY WITH SYMMETRIC LEAKAGE-COMPENSATED BIT LINE
    7.
    发明申请
    STATIC RANDOM ACCESS MEMORY WITH SYMMETRIC LEAKAGE-COMPENSATED BIT LINE 审中-公开
    具有对称泄漏补偿位线的静态随机存取存储器

    公开(公告)号：WO2004025661A2

    公开(公告)日：2004-03-25

    申请号：PCT/US0327789

    申请日：2003-09-05

    Applicant: INTEL CORP

    Inventor： ALVANDPOUR ATILA ,  SOMASEKHAR DINESH ,  HSU STEVEN ,  KRISHNAMURTY RAM ,  DE VIVEK

    IPC: G11C11/412 ,  G11C11/419

    CPC classification number: G11C11/412 ,  G11C11/419

    Abstract: An eight-cell memory cell for static random access memory, the memory cell comprising cross-coupled inverters to store the information bit, two access nMOSFETs connected to local bit lines to access the stored information bit, and two nMOSFETs each having a gate connected to ground and coupled to the local bit lines and the cross-coupled inverters so that sub-threshold leakage currents to and from the local bit lines for a memory cell not being read are balanced.

    Abstract translation: 一种用于静态随机存取存储器的八单元存储单元，该存储单元包括交叉耦合的反相器以存储信息位，连接到局部位线以访问存储的信息位的两个存取nMOSFET，以及两个nMOSFET，每个nMOSFET具有连接到 并且耦合到本地位线和交叉耦合的反相器，使得用于未被读取的存储单元的去往和来自局部位线的亚阈值泄漏电流被平衡。

    NOR LOGIC WORD LINE SELECTION
    9.
    发明申请
    NOR LOGIC WORD LINE SELECTION 审中-公开
    NOR逻辑字行选择

    公开(公告)号：WO2012087473A3

    公开(公告)日：2012-08-16

    申请号：PCT/US2011061607

    申请日：2011-11-21

    Applicant: INTEL CORP ,  GHOSH SWAROOP ,  SOMASEKHAR DINESH ,  SRINIVASAN BALAJI ,  HAMZAOGLU FATIH

    Inventor： GHOSH SWAROOP ,  SOMASEKHAR DINESH ,  SRINIVASAN BALAJI ,  HAMZAOGLU FATIH

    IPC: G11C11/4063

    CPC classification number: G11C11/4085 ,  G11C8/08 ,  G11C8/10 ,  G11C16/08

    Abstract: A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.

    Abstract translation: 公开了用于在DRAM中选择字线驱动器的NOR架构。 在低，中和高范围中单独解码地址的补码用于选择最终的字线驱动器。 字线驱动器的输出对于未选中的字线而言处于相对于地的负电位，并且对于所选字线而言，正电位比电源电位更正。

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