公开(公告)号：JP2014225242A

公开(公告)日：2014-12-04

申请号：JP2014052039

申请日：2014-03-14

Applicant: インテル・コーポレーション ,  Intel Corp

Inventor： ELIERZER WEISSMANN ,  RINAT RAPPOPORT ,  MICHAEL MISHAELI ,  HISHAM SHAFI ,  ORON LENZ ,  JASON W BRANDT ,  STEPHEN A FISCHER ,  TOLL BRET L ,  SOJI INGDA EM ,  ALON NAVEH ,  GANAPATI N SRINIVASA ,  ASHISH V CHOUBAL ,  SCOTT D HAHN ,  DAVID A KOUFATY ,  RUSSEL J FENGER ,  GAURAV KHANNA ,  EUGENE GORBATOV ,  MISHALI NAIK ,  ANDREW J HERDRICH ,  ABIRAMI PRABHAKARAN ,  SANJEEV S JAHAGIRDAR ,  PAUL BRETT ,  PAOLO NARVAEZ ,  ANDREW D HENROID ,  DHEERAJ R SUBBAREDDY

IPC: G06F9/445 ,  G06F1/32 ,  G06F9/46 ,  G06F9/50

CPC classification number: G06F9/4401 ,  G06F9/45558 ,  G06F9/5077 ,  Y02B60/142 ,  Y02B60/167 ,  Y02D10/22 ,  Y02D10/36

Abstract: 【課題】ソフトウェアが使用可能な異なる種類のCPUコアを把握して異種性を効果的に利用出来るようにする。【解決手段】1組の大きな物理プロセッサコア804と、大きな物理プロセッサコアに比べて比較的低い処理能力および比較的低い電力使用を有する1組の小さな物理プロセッサコア802と、ブートストラッププロセッサをイネーブルとするパッケージユニット805とを含み、ブートストラッププロセッサは同種の物理プロセッサコアを初期化し、異種プロセッサがシステムファームウェアインタフェースにとって同種のプロセッサに見えるようにする。【選択図】図8

Abstract translation: 要解决的问题：使软件能够掌握不同类型的可用CPU内核并有效利用异构性。解决方案：一个实施例包括：一组大型物理处理器核804; 一组小型物理处理器核802具有比大型物理处理器核更低的处理能力和更低的功率使用; 以及包装单元805，以使能引导处理器。 引导处理器初始化同构物理处理器内核，而异构处理器将同构处理器的外观呈现给系统固件界面。

公开(公告)号：BR102014006299A8

公开(公告)日：2018-05-29

申请号：BR102014006299

申请日：2014-03-17

Applicant: INTEL CORP

Inventor： ABIRAMI PRABHAKARAN ,  ALON NAVEH ,  ANDREW D HENROID ,  ANDREW J HERDRICH ,  ASHISH V CHOUBAL ,  BRET L TOLL ,  DAVID A KOUFATY ,  DHEERAJ R SUBBAREDDY ,  ELIERZER WEISSMANN ,  EUGENE GORBATOV ,  GANAPATI N SRINIVASA ,  GAURAV KHANNA ,  HISHAM SHAFI ,  INDER M SODHI ,  JASON W BRANDT ,  MICHAEL MISHAELI ,  MISHALI NAIK ,  ORON LENZ ,  PAOLO NARVAEZ ,  PAUL BRETT ,  RIMAT RAPPOPORT ,  RUSSEL J FENGER ,  SANJEEV S JAHAGIRDAR ,  SCOTT D HAHN ,  STEPHEN A FICHER

IPC: G06F9/44 ,  G06F9/455 ,  G06F9/50

Abstract: método para inicializar um sistema heterogêneo e apresentar uma vista simétrica do núcleo. a presente invenção descreve uma arquitetura de processador heterogêneo e um método de inicialização de um processador heterogêneo. um processador de acordo com uma modalidade compreende: um conjunto de núcleos grandes de processador físico; um conjunto de núcleos pequenos de processador físico, tendo capacidade de processamento com desempenho relativamente mais baixo e uso de energia relativamente menor em relação aos núcleos grandes de processador físico; e uma unidade de pacote para habilitar um processador bootstrap. o processador bootstrap inicializa os núcleos do processador físico homogêneo, enquanto o processador heterogêneo apresenta a aparência de um processador homogêneo para uma interface de firmware do sistema

公开(公告)号：GB2547769B

公开(公告)日：2018-04-25

申请号：GB201700245

申请日：2014-03-14

Applicant: INTEL CORP

Inventor： ELIERZER WEISSMANN ,  RINAT RAPPOPORT ,  MICHAEL MISHAELI ,  HISHAM SHAFI ,  ORON LENZ ,  JASON W BRANDT ,  STEPHEN A FISCHER ,  BRET L TOLL ,  INDER M SODHI ,  ALON NAVEH ,  GANAPATI SRINIVASA ,  ASHISH CHOUBAL ,  SCOTT D HAHN ,  DAVID A KOUFATY ,  RUSSEL J FENGER ,  GAURAV KHANNA ,  EUGENE GORBATOV ,  MISHALI NAIK ,  ANDREW J HERDRICH ,  ABIRAMI PRABHAKARAN ,  SANJEEV JAHAGIRDAR ,  PAUL BRETT ,  PAOLO NARVAEZ ,  ANDREW D HENROID ,  DHEERAJ R SUBBAREDDY

IPC: G06F9/50 ,  G06F1/32

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

公开(公告)号：GB2547769A

公开(公告)日：2017-08-30

申请号：GB201700245

申请日：2014-03-14

Applicant: INTEL CORP

Inventor： ELIERZER WEISSMANN ,  RINAT RAPPOPORT ,  MICHAEL MISHAELI ,  HISHAM SHAFI ,  ORON LENZ ,  JASON W BRANDT ,  STEPHEN A FISCHER ,  BRET L TOLL ,  INDER M SODHI ,  ALON NAVEH ,  GANAPATI SRINIVASA ,  ASHISH CHOUBAL ,  SCOTT D HAHN ,  DAVID A KOUFATY ,  RUSSEL J FENGER ,  GAURAV KHANNA ,  EUGENE GORBATOV ,  MISHALI NAIK ,  ANDREW J HERDRICH ,  ABIRAMI PRABHAKARAN ,  SANJEEV JAHAGIRDAR ,  PAUL BRETT ,  PAOLO NARVAEZ ,  ANDREW D HENROID ,  DHEERAJ R SUBBAREDDY

IPC: G06F9/50 ,  G06F1/32

Abstract: A heterogeneous processor comprises a first physical core having a first instruction set and a first power consumption level, to execute at a first performance level, and a second physical core having a second instruction set and a second power consumption level, to execute at a second performance level. The first and second cores are in a dynamic multi-core unit. A mapping circuit is coupled to the first and second physical cores. The first physical core is mapped to a system firmware interface via a first virtual core, and the second physical core is hidden from the system software. The first physical core may act as a bootstrap processor and this may initialize the second physical core. The second physical core may only be accessible via specialized microcode routines. The system software may include the firmware interface and an operating system.

公开(公告)号：GB2514236B

公开(公告)日：2017-02-15

申请号：GB201404549

申请日：2014-03-14

Applicant: INTEL CORP

Inventor： ELIERZER WEISSMANN ,  RINAT RAPPOPORT ,  MICHAEL MISHAELI ,  HISHAM SHAFI ,  ORON LENZ ,  JASON W BRANDT ,  STEPHEN A FISCHER ,  BRET L TOLL ,  INDER M SODHI ,  ALON NAVEH ,  GANAPATI SPRINIVASA ,  ASHISH CHOUBAL ,  SCOTT D HAHN ,  DAVID A KOUFATY ,  RUSSEL J FENGER ,  GAURAV KHANNA ,  EUGENE GORBATOV ,  MISHALI NAIK ,  ANDREW J HERDRICH ,  ABIRAMI PRABHAKARAN ,  SANJEEV JAHAGIRDAR ,  PAUL BRETT ,  PAOLO NARVAEZ ,  ANDREW D HENROID ,  DHEERAJ R SUBBAREDDY

IPC: G06F9/50 ,  G06F1/32

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

公开(公告)号：GB2510091B

公开(公告)日：2020-05-20

申请号：GB201408838

申请日：2011-12-30

Applicant: INTEL CORP

Inventor： GUY M THERIEN ,  PAUL S DIEFENBAUGH ,  ANIL AGGARWAL ,  ANDREW D HENROID ,  JEREMY J SHRALL ,  EFRAIM ROTEM ,  KRISHNAKANTH SISTLA ,  ELIERZER WEISSMANN

IPC: G06F1/3203 ,  G06F1/324 ,  G06F1/3296

Abstract: In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data.