公开(公告)号：HK1006884A1

公开(公告)日：1999-03-19

申请号：HK98105915

申请日：1998-06-22

Applicant: INTEL CORP

Inventor： MATTER EUGENE P ,  FARRER STEVEN M

IPC: G06F12/06 ,  G06F12/02 ,  G11C11/4076 ,  G06F

Abstract: A memory controller for a dynamic random access memory (DRAM) is described. The memory controller of the present invention provides access to a memory array which uses DRAM banks. The memory controller is adaptable to various types of DRAM banks, such that the memory array is capable of having independent and different configurations of DRAM banks in the memory. The memory controller includes multiple programmable storage registers, where one register is associated with every bank location in the memory array. Each of the programmable registers is independently programmed to contain access parameters that are necessary to access its associated bank. The memory controller of the present invention also includes circuitry which is configured to provide each of the banks in the memory with its necessary control signals in the proper sequence and timing according to the access parameters in its associated storage register. In this manner, the present invention is capable of accommodating DRAM banks of different types in the memory array.

公开(公告)号：GB2264799A

公开(公告)日：1993-09-08

申请号：GB9305800

申请日：1993-03-19

Applicant: INTEL CORP

Inventor： REDDY CHANDRASHEKAR M ,  HIROSE SCOTT D ,  CHO SUNG-SOO ,  KARDACH JAMES P ,  FARRER STEVEN M ,  ROBERTS MEELING

IPC: G06F1/04 ,  G06F1/32 ,  G06F15/78 ,  G11C11/401 ,  G11C11/406

Abstract: A power suspend mode activates a slow DRAM refresh in a computer system (10) with a limited source of power. The power suspend (100) mode reduces the power consumed by the computer system (10) while preserving the contents of memory. The cyclic refresh of DRAM (80) using a slow refresh clock substantially reduces the power consumed while the computer is suspended. This technique is particularly useful for battery powered portable computer systems. When an external or internal condition causes the computer system to transition to a power down mode, an IO subsystem (30) notifies the CPU (20) which sets control bits in the IO (30) subsystem and a video subsystem (40). The IO subsystem (30) then begins to generate a slow DRAM refresh pulse (91). Once the CPU (20) and video subsystem (40) sense the power suspend mode activation, the system memory (80) and video memory (50) are refreshed using the slow refresh clock. The power consumed during the refresh process is thereby greatly reduced. When a resume signal is received by the IO subsystem (30), the slow refresh clock (91) is terminated and the system memory (80) and video memory (50) are again refreshed using a normal faster clock.

公开(公告)号：GB2271003B

公开(公告)日：1996-02-14

申请号：GB9313110

申请日：1993-06-25

Applicant: INTEL CORP

Inventor： FARRER STEVEN M ,  MATTER EUGENE P

IPC: G06F12/06 ,  G06F12/02 ,  G11C11/4076 ,  G06F12/00

Abstract: A memory controller for a dynamic random access memory (DRAM) is described. The memory controller of the present invention provides access to a memory array which uses DRAM banks. The memory controller is adaptable to various types of DRAM banks, such that the memory array is capable of having independent and different configurations of DRAM banks in the memory. The memory controller includes multiple programmable storage registers, where one register is associated with every bank location in the memory array. Each of the programmable registers is independently programmed to contain access parameters that are necessary to access its associated bank. The memory controller of the present invention also includes circuitry which is configured to provide each of the banks in the memory with its necessary control signals in the proper sequence and timing according to the access parameters in its associated storage register. In this manner, the present invention is capable of accommodating DRAM banks of different types in the memory array.

公开(公告)号：GB2264799B

公开(公告)日：1994-11-16

申请号：GB9305800

申请日：1993-03-19

Applicant: INTEL CORP

Inventor： REDDY CHANDRASHEKAR M ,  HIROSE SCOTT D ,  CHO SUNG-SOO ,  KARDACH JAMES P ,  FARRER STEVEN M ,  ROBERTS MEELING

IPC: G06F1/04 ,  G06F1/32 ,  G06F15/78 ,  G11C11/401 ,  G11C11/406

Abstract: A power suspend mode activates a slow DRAM refresh in a computer system with a limited source of power. The power suspend mode reduces the power consumed by the computer system while preserving the contents of memory. The cyclic refresh of DRAM using a slow refresh clock substantially reduces the power consumed while the computer is suspended. This technique is particularly useful for battery powered portable computer systems. When an external or internal condition causes the computer system to transition to a power down mode, an IO subsystem notifies the CPU which sets control bits in the IO subsystem and a video subsystem. The IO subsystem then begins to generate a slow DRAM refresh pulse. Once the CPU and video subsystem sense the power suspend mode activation, the system memory and video memory are refreshed using the slow refresh clock. The power consumed during the refresh process is thereby greatly reduced. When a resume signal is received by the IO subsystem, the slow refresh clock is terminated and the system memory and video memory are again refreshed using a normal faster clock.

公开(公告)号：GB2271003A

公开(公告)日：1994-03-30

申请号：GB9313110

申请日：1993-06-25

Applicant: INTEL CORP

Inventor： FARRER STEVEN M ,  MATTER EUGENE P

IPC: G06F12/06 ,  G06F12/02 ,  G11C11/4076 ,  G06F12/00

Abstract: A memory controller provides access to a memory array which uses DRAM banks. The memory controller is adaptable to various types of DRAM banks, such that the memory array is capable of having independent and different configurations of DRAM banks in the memory. The memory controller includes multiple programmable storage registers, where one register is associated with every bank location in the memory array. Each of the programmable registers is independently programmed to contain access parameters that are necessary to access its associated bank. The memory controller also includes circuitry which is configured to provide each of the banks in the memory with its necessary control signals in the proper sequence and timing according to the access parameters in its associated storage register. In this manner, different types of DRAM banks can be accommodated in the memory array.

公开(公告)号：HK66295A

公开(公告)日：1995-05-12

申请号：HK66295

申请日：1995-05-04

Applicant: INTEL CORP

Inventor： REDDY CHANDRASHEKAR M ,  HIROSE SCOTT D ,  CHO SUNG-SOO ,  KARDACH JAMES P ,  FARRER STEVEN M ,  ROBERTS MEELING

IPC: G06F1/04 ,  G06F1/32 ,  G06F15/78 ,  G11C11/401 ,  G11C11/406

Abstract: A power suspend mode activates a slow DRAM refresh in a computer system with a limited source of power. The power suspend mode reduces the power consumed by the computer system while preserving the contents of memory. The cyclic refresh of DRAM using a slow refresh clock substantially reduces the power consumed while the computer is suspended. This technique is particularly useful for battery powered portable computer systems. When an external or internal condition causes the computer system to transition to a power down mode, an IO subsystem notifies the CPU which sets control bits in the IO subsystem and a video subsystem. The IO subsystem then begins to generate a slow DRAM refresh pulse. Once the CPU and video subsystem sense the power suspend mode activation, the system memory and video memory are refreshed using the slow refresh clock. The power consumed during the refresh process is thereby greatly reduced. When a resume signal is received by the IO subsystem, the slow refresh clock is terminated and the system memory and video memory are again refreshed using a normal faster clock.

公开(公告)号：AU8908691A

公开(公告)日：1992-05-20

申请号：AU8908691

申请日：1991-10-11

Applicant: INTEL CORP

Inventor： REDDY CHANDRASHEKAR M ,  HIROSE SCOTT D ,  CHO SUNG-SOO ,  KARDACH JAMES P ,  FARRER STEVEN M ,  ROBERTS MEELING

IPC: G06F1/04 ,  G06F1/32 ,  G06F15/78 ,  G11C11/401 ,  G11C11/406 ,  G06F1/26

Abstract: A power suspend mode activates a slow DRAM refresh in a computer system with a limited source of power. The power suspend mode reduces the power consumed by the computer system while preserving the contents of memory. The cyclic refresh of DRAM using a slow refresh clock substantially reduces the power consumed while the computer is suspended. This technique is particularly useful for battery powered portable computer systems. When an external or internal condition causes the computer system to transition to a power down mode, an IO subsystem notifies the CPU which sets control bits in the IO subsystem and a video subsystem. The IO subsystem then begins to generate a slow DRAM refresh pulse. Once the CPU and video subsystem sense the power suspend mode activation, the system memory and video memory are refreshed using the slow refresh clock. The power consumed during the refresh process is thereby greatly reduced. When a resume signal is received by the IO subsystem, the slow refresh clock is terminated and the system memory and video memory are again refreshed using a normal faster clock.