公开(公告)号：WO2010060084A2

公开(公告)日：2010-05-27

申请号：PCT/US2009065735

申请日：2009-11-24

Applicant: INTEL CORP ,  LATORRE FERNANDO ,  CODINA JOSEP M ,  GIBERT ENRIC ,  LOPEZ PEDRO ,  MADRILES CARLOS ,  MARTINEZ ALEJANDRO ,  MARTINEZ RAUL ,  GONZALEZ ANTONIO

Inventor： LATORRE FERNANDO ,  CODINA JOSEP M ,  GIBERT ENRIC ,  LOPEZ PEDRO ,  MADRILES CARLOS ,  MARTINEZ ALEJANDRO ,  MARTINEZ RAUL ,  GONZALEZ ANTONIO

IPC: G06F9/30 ,  G06F12/00 ,  G06F13/00

CPC classification number: G06F9/3842 ,  G06F8/433 ,  G06F8/452 ,  G06F8/457 ,  G06F9/3851 ,  G06F9/3861

Abstract: Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC.

Abstract translation: 描述了用于将顺序程序分解成多个线程，执行这些线程以及重建线程的顺序执行的系统，方法和装置。 多个数据高速缓存单元（DCU）存储推测执行的线程的本地退役指令。 合并级别缓存（MLC）合并来自DCU的行的数据。 核心间存储器一致性模块（ICMC）全局退避MLC中推测执行的线程的指令。

公开(公告)号：DE112006004005T5

公开(公告)日：2009-06-10

申请号：DE112006004005

申请日：2006-10-27

Applicant: INTEL CORP

Inventor： GIBERT ENRIC ,  CODINA JOSEP M ,  LATORRE FERNANDO ,  PINEIRO JOSE ALEJANDRO ,  LOPEZ PEDRO ,  GONZALEZ ANTONIO

IPC: G06F9/46 ,  G06F9/54

Abstract: In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a second thread from executing if a synchronization indicator associated with the source operand indicates incompletion of a producer operation of the second thread, and executing the instruction if the synchronization indicator indicates completion of the producer operation of the second thread. Other embodiments are described and claimed.