公开(公告)号：JP2010244544A

公开(公告)日：2010-10-28

申请号：JP2010080729

申请日：2010-03-31

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： LOPEZ PEDRO ,  MADRILES CARLOS ,  MARTINEZ ALEJANDRO ,  MARTINEZ RAUL ,  CODINA JOSEPH M ,  CODINA ENRIC GIBERT ,  LATORRE FERNANDO ,  GONZALEZ ANTONIO

IPC: G06F9/46 ,  G06F9/52

CPC classification number: G06F9/3863 ,  G06F9/30043 ,  G06F9/3842 ,  G06F9/3851 ,  G06F11/1402

Abstract: PROBLEM TO BE SOLVED: To resolve multithreading mis-speculation.
SOLUTION: A number of multiple thread units concurrently execute threads. They execute a checkpoint mask instruction to initialize memory to store active checkpoint data including register contents and a checkpoint mask indicating the validity of stored register contents. As register contents change, threads execute checkpoint write instructions to store register contents and update the checkpoint mask. The threads also execute a recovery function instruction to store a pointer to a checkpoint recovery function, and in response to mis-speculation among the threads, branch to the checkpoint recovery function. The threads then execute one or more checkpoint read instructions to copy data from a valid checkpoint storage area into the registers necessary to recover a valid architectural state, from which execution may resume.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：解决多线程错误猜测。

解决方案：多个线程单元同时执行线程。 它们执行检查点掩码指令来初始化存储器以存储包括寄存器内容的活动检查点数据和指示存储的寄存器内容的有效性的检查点掩码。 随着寄存器内容的改变，线程执行检查点写入指令来存储寄存器内容并更新检查点掩码。 线程还执行恢复功能指令来存储指向检查点恢复功能的指针，并且响应于线程之间的错误猜测，分支到检查点恢复功能。 线程然后执行一个或多个检查点读取指令以将数据从有效的检查点存储区域复制到恢复有效架构状态所需的寄存器中，从该执行可以恢复。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：DE112006003917T5

公开(公告)日：2009-06-04

申请号：DE112006003917

申请日：2006-05-30

Applicant: INTEL CORP

Inventor： GIMENO CARLOS MADRILES ,  QUINONES CARLOS GARCIA ,  MARCUELLO PEDRO ,  SANCHEZ JESES ,  LATORRE FERNANDO ,  GONZALEZ ANTONIO

IPC: G06F12/08 ,  G06F12/0831

Abstract: In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thread and a first thread associated with the first cache with respect to the portion. Other embodiments are described and claimed.

公开(公告)号：WO2013101078A8

公开(公告)日：2013-09-06

申请号：PCT/US2011067865

申请日：2011-12-29

Applicant: INTEL CORP ,  GIBERT CODINA ENRIC ,  LATORRE FERNANDO ,  CODINA JOSEP M ,  GOMEZ REQUENA CRISPIN ,  GONZALEZ ANTONIO ,  HYUSEINOVA MEYREM ,  KOTSELIDIS CHRISTOS E ,  LOPEZ PEDRO ,  LUPON MARC ,  MADRILES CARLOS ,  MAGKLIS GRIGORIOS ,  MARCUELLO PEDRO ,  MARTINEZ VICENTE ALEJANDRO ,  MARTINEZ RAUL ,  ORTEGA DANIEL ,  PAVLOU DEMOS ,  STAVROU KYRIAKOS A ,  TOURNAVITIS GEORGIOS ,  XEKALAKIS POLYCHRONIS

Inventor： GIBERT CODINA ENRIC ,  LATORRE FERNANDO ,  CODINA JOSEP M ,  GOMEZ REQUENA CRISPIN ,  GONZALEZ ANTONIO ,  HYUSEINOVA MEYREM ,  KOTSELIDIS CHRISTOS E ,  LOPEZ PEDRO ,  LUPON MARC ,  MADRILES CARLOS ,  MAGKLIS GRIGORIOS ,  MARCUELLO PEDRO ,  MARTINEZ VICENTE ALEJANDRO ,  MARTINEZ RAUL ,  ORTEGA DANIEL ,  PAVLOU DEMOS ,  STAVROU KYRIAKOS A ,  TOURNAVITIS GEORGIOS ,  XEKALAKIS POLYCHRONIS

IPC: G06F9/06 ,  G06F12/08

CPC classification number: G06F12/0815 ,  G06F2212/507

Abstract: Techniques are described for providing an enhanced cache coherency protocol for a multi-core processor that includes a Speculative Request For Ownership Without Data (SRFOWD) for a portion of cache memory. With a SRFOWD, only an acknowledgement message may be provided as an answer to a requesting core. The contents of the affected cache line are not required to be a part of the answer. The enhanced cache coherency protocol may assure that a valid copy of the current cache line exists in case of misspeculation by the requesting core. Thus, an owner of the current copy of the cache line may maintain a copy of the old contents of the cache line. The old contents of the cache line may be discarded if speculation by the requesting core turns out to be correct. Otherwise, in case of misspeculation by the requesting core, the old contents of the cache line may be set back to a valid state.

Abstract translation: 描述了用于为多核处理器提供增强的高速缓存一致性协议的技术，所述多核处理器包括用于高速缓冲存储器的一部分的无数据的所有权投标请求（SRFOWD）。 使用SRFOWD，可以仅提供确认消息作为请求内核的答案。 受影响的缓存行的内容不需要作为答案的一部分。 增强的高速缓存一致性协议可以确保在请求核心的错误配置的情况下存在当前高速缓存行的有效副本。 因此，高速缓存行的当前副本的所有者可以维护高速缓存行的旧内容的副本。 如果请求的核心的猜测证明是正确的，则可以丢弃该高速缓存行的旧内容。 否则，在请求核心发生错误的情况下，可以将高速缓存行的旧内容设置回有效状态。

公开(公告)号：WO2010060084A2

公开(公告)日：2010-05-27

申请号：PCT/US2009065735

申请日：2009-11-24

Applicant: INTEL CORP ,  LATORRE FERNANDO ,  CODINA JOSEP M ,  GIBERT ENRIC ,  LOPEZ PEDRO ,  MADRILES CARLOS ,  MARTINEZ ALEJANDRO ,  MARTINEZ RAUL ,  GONZALEZ ANTONIO

Inventor： LATORRE FERNANDO ,  CODINA JOSEP M ,  GIBERT ENRIC ,  LOPEZ PEDRO ,  MADRILES CARLOS ,  MARTINEZ ALEJANDRO ,  MARTINEZ RAUL ,  GONZALEZ ANTONIO

IPC: G06F9/30 ,  G06F12/00 ,  G06F13/00

CPC classification number: G06F9/3842 ,  G06F8/433 ,  G06F8/452 ,  G06F8/457 ,  G06F9/3851 ,  G06F9/3861

Abstract: Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC.

Abstract translation: 描述了用于将顺序程序分解成多个线程，执行这些线程以及重建线程的顺序执行的系统，方法和装置。 多个数据高速缓存单元（DCU）存储推测执行的线程的本地退役指令。 合并级别缓存（MLC）合并来自DCU的行的数据。 核心间存储器一致性模块（ICMC）全局退避MLC中推测执行的线程的指令。

公开(公告)号：DE102015007943A1

公开(公告)日：2016-01-28

申请号：DE102015007943

申请日：2015-06-19

Applicant: INTEL CORP

Inventor： FALCON AYOSE J ,  LUPON MARC ,  HERRERO ABELLANAS ENRIC ,  LATORRE FERNANDO ,  LOPEZ PEDRO ,  TOURNAVITIS GEORGIOS ,  PRATAS FREDERICO C

IPC: G06N3/02

Abstract: Ein Prozessor umfasst einen Prozessorkern und einen Berechnungsschaltkreis. Der Prozessorkern umfasst eine Logik zum Bestimmen eines Satzes von Gewichtungen zur Verwendung in einer Berechnung für ein faltendes neuronales Netzwerk (Convolutional Neural Network, CNN) und zum Hochskalieren der Gewichtungen mithilfe eines Skalierungswertes. Der Berechnungsschaltkreis umfasst eine Logik zum Empfangen des Skalierungswertes, des Satzes von Gewichtungen und eines Satzes von Eingangswerten, wobei jeder Eingangswert und die zugehörige Gewichtung die gleiche Größe aufweisen. Der Berechnungsschaltkreis umfasst auch eine Logik zum Ermitteln von Ergebnissen aus den Berechnungen für ein faltendes neuronales Netzwerk (CNN) auf der Grundlage des Satzes von Gewichtungen, der auf den Satz von Eingangswerten angewandt wurde, zum Herunterskalieren der Ergebnisse mithilfe des Skalierungswertes, zum Kürzen der herunterskalierten Werte auf die feste Größe und zum Verbinden der gekürzten Ergebnisse für einen Datenaustausch mit einer Ausgabe für eine Schicht des CNN.

公开(公告)号：DE112006004005T5

公开(公告)日：2009-06-10

申请号：DE112006004005

申请日：2006-10-27

Applicant: INTEL CORP

Inventor： GIBERT ENRIC ,  CODINA JOSEP M ,  LATORRE FERNANDO ,  PINEIRO JOSE ALEJANDRO ,  LOPEZ PEDRO ,  GONZALEZ ANTONIO

IPC: G06F9/46 ,  G06F9/54

Abstract: In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a second thread from executing if a synchronization indicator associated with the source operand indicates incompletion of a producer operation of the second thread, and executing the instruction if the synchronization indicator indicates completion of the producer operation of the second thread. Other embodiments are described and claimed.

公开(公告)号：EP2798470A4

公开(公告)日：2015-07-15

申请号：EP11878987

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： STAVROU KYRIAKOS A ,  GIBERT CODINA ENRIC ,  CODINA JOSEP M ,  GOMEZ REQUENA CRISPIN ,  GONZALEZ ANTONIO ,  HYUSEINOVA MIREM ,  KOTSELIDIS CHRISTOS E ,  LATORRE FERNANDO ,  LOPEZ PEDRO ,  LUPON MARC ,  MADRILES CARLOS ,  MAGKLIS GRIGORIOS ,  MARCUELLO PEDRO ,  MARTINEZ VICENTE ALEJANDRO ,  MARTINEZ RAUL ,  ORTEGA DANIEL ,  PAVLOU DEMOS ,  TOURNAVITIS GEORGIOS ,  XEKALAKIS POLYCHRONIS

IPC: G06F9/06 ,  G06F9/30

CPC classification number: G06F9/3804 ,  G06F9/30047 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3848 ,  G06F12/0862 ,  G06F2212/452

Abstract: Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.

Abstract translation: 公开了一种用于从指令高速缓存管理指令高速缓存预取的装置和方法。 处理器可以包括：预取引擎; 预测分支结果的分支预测引擎; 和动态优化器。 动态优化器可用于控制：识别公共指令高速缓存未命中，并将预取引擎的预取指令插入指令高速缓存。

公开(公告)号：EP2798520A4

公开(公告)日：2016-12-07

申请号：EP11878906

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： MAGKLIS GRIGORIOS ,  CODINA JOSEP M ,  ZILLES CRAIG B ,  NEILLY MICHAEL ,  SAMUDRALA SRIDHAR ,  MARTINEZ VICENTE ALEJANDRO ,  XEKALAKIS POLYCHRONIS ,  SANCHEZ F JESUS ,  LUPON MARC ,  TOURNAVITIS GEORGIOS ,  GIBERT CODINA ENRIC ,  GOMEZ REQUENA CRISPIN ,  GONZALEZ ANTONIO ,  HYUSEINOVA MIREM ,  KOTSELIDIS CHRISTOS E ,  LATORRE FERNANDO ,  LOPEZ PEDRO ,  MADRILES CARLOS ,  MARCUELLO PEDRO ,  MARTINEZ RAUL ,  ORTEGA DANIEL ,  PAVLOU DEMOS ,  STAVROU KYRIAKOS A

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3001 ,  G06F9/30032 ,  G06F9/30087 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3842