公开(公告)号：WO2012009150A3

公开(公告)日：2012-04-05

申请号：PCT/US2011041987

申请日：2011-06-27

Applicant: INTEL CORP ,  NEMIROFF DANIEL ,  VEMBU BALAJI ,  GUTIERREZ RAHUL ,  KAREENAHALLI SURYAPRASAD

Inventor： NEMIROFF DANIEL ,  VEMBU BALAJI ,  GUTIERREZ RAHUL ,  KAREENAHALLI SURYAPRASAD

IPC: G06F12/00 ,  G06F9/06 ,  G06F13/28

CPC classification number: G06F9/5027

Abstract: The architecture and techniques described herein can improve system performance with respect to the following. Communication between two interdependent hardware engines, that are part of pipeline, such that the engines are synchronized to consume resources when the engines are done with the work. Reduction of the role of software/firmware from feeding each stage of the hardware pipeline when the previous stage of the pipeline has completed. Reduction in the memory allocation for software-initialized hardware descriptors to improve performance by reducing pipeline stalls due to software interaction.

Abstract translation: 本文描述的架构和技术可以改善系统性能。 两个相互依赖的硬件引擎之间的通信是管道的一部分，使得引擎在引擎完成工作时同步以消耗资源。 当管道的上一个阶段完成时，减少软件/固件从硬件管道的每个阶段的角色。 减少用于软件初始化的硬件描述符的内存分配，以通过减少由于软件交互而导致的流水线停顿来提高性能。

公开(公告)号：EP2585923A4

公开(公告)日：2016-05-18

申请号：EP11807267

申请日：2011-06-27

Applicant: INTEL CORP

Inventor： NEMIROFF DANIEL ,  VEMBU BALAJI ,  GUTIERREZ RAHUL ,  KAREENAHALLI SURYAPRASAD

IPC: G06F12/00 ,  G06F9/06 ,  G06F13/28 ,  G06T1/20

CPC classification number: G06F9/5027

Abstract: The architecture and techniques described herein can improve system performance with respect to the following. Communication between two interdependent hardware engines, that are part of pipeline, such that the engines are synchronized to consume resources when the engines are done with the work. Reduction of the role of software/firmware from feeding each stage of the hardware pipeline when the previous stage of the pipeline has completed. Reduction in the memory allocation for software-initialized hardware descriptors to improve performance by reducing pipeline stalls due to software interaction.