BOUNDARY DETECTION IN MEDIA STREAMS
    1.
    发明申请
    BOUNDARY DETECTION IN MEDIA STREAMS 审中-公开
    媒体流域的边界检测

    公开(公告)号:WO2011139476A3

    公开(公告)日:2012-03-08

    申请号:PCT/US2011031699

    申请日:2011-04-08

    CPC classification number: G11B27/3027 G11B27/28

    Abstract: Encoded data decoding techniques. A data decoding agent determines a data segment size for a packet that includes a header and a data segment. The data decoding agent determines a segment end location based, at least in part, on the data segment size. The data decoding agent processes subblocks of data from the data segment. The data decoding agent compares a current location to the segment end location to determine if a current subblock of data from the data segments contains the segment end location. The data decoding agent triggers an exception handler if the current subblock contains the segment end location.

    Abstract translation: 编码数据解码技术。 数据解码代理确定包括报头和数据段的分组的数据段大小。 数据解码代理至少部分地基于数据段大小来确定段结束位置。 数据解码代理处理来自数据段的数据的子块。 数据解码代理将当前位置与段结束位置进行比较,以确定来自数据段的当前数据子块是否包含段结束位置。 如果当前子块包含段结束位置,则数据解码代理触发异常处理程序。

    DIRECT MEMORY ACCESS ENGINE PHYSICAL MEMORY DESCRIPTORS FOR MULTI-MEDIA DEMULTIPLEXING OPERATIONS
    2.
    发明申请
    DIRECT MEMORY ACCESS ENGINE PHYSICAL MEMORY DESCRIPTORS FOR MULTI-MEDIA DEMULTIPLEXING OPERATIONS 审中-公开
    直接存储器访问引擎用于多媒体解复用操作的物理存储器描述符

    公开(公告)号:WO2012009150A3

    公开(公告)日:2012-04-05

    申请号:PCT/US2011041987

    申请日:2011-06-27

    CPC classification number: G06F9/5027

    Abstract: The architecture and techniques described herein can improve system performance with respect to the following. Communication between two interdependent hardware engines, that are part of pipeline, such that the engines are synchronized to consume resources when the engines are done with the work. Reduction of the role of software/firmware from feeding each stage of the hardware pipeline when the previous stage of the pipeline has completed. Reduction in the memory allocation for software-initialized hardware descriptors to improve performance by reducing pipeline stalls due to software interaction.

    Abstract translation: 本文描述的架构和技术可以改善系统性能。 两个相互依赖的硬件引擎之间的通信是管道的一部分,使得引擎在引擎完成工作时同步以消耗资源。 当管道的上一个阶段完成时,减少软件/固件从硬件管道的每个阶段的角色。 减少用于软件初始化的硬件描述符的内存分配,以通过减少由于软件交互而导致的流水线停顿来提高性能。

    METHODS AND APPARATUSES FOR SECURING PLAYBACK CONTENT
    3.
    发明申请
    METHODS AND APPARATUSES FOR SECURING PLAYBACK CONTENT 审中-公开
    保护播放内容的方法和装置

    公开(公告)号:WO2011156066A3

    公开(公告)日:2012-02-16

    申请号:PCT/US2011035412

    申请日:2011-05-05

    Abstract: An apparatus for secured playback is presented. In one embodiment, the apparatus includes a controller that includes a key derivation module to manage authentication and key derivation. In one embodiment, the apparatus provides a video decryption key to a graphics engine if video data portions in a data stream are retrievable without having to decrypt the data stream. In one embodiment, the apparatus also includes a decryption module to decrypt a part of data in conjunction with an encryption key to generate video information and video data. The controller then writes an encrypted version of the video data to a video buffer of a graphics engine.

    Abstract translation: 提出了一种用于安全播放的设备。 在一个实施例中,该装置包括控制器,其包括用于管理认证和密钥推导的密钥导出模块。 在一个实施例中,如果可以检索数据流中的视频数据部分而不必对数据流进行解密,则该装置向图形引擎提供视频解密密钥。 在一个实施例中,该装置还包括解密模块,用于结合加密密钥对一部分数据进行解密以产生视频信息和视频数据。 然后,控制器将视频数据的加密版本写入图形引擎的视频缓冲器。

    5.
    发明专利
    未知

    公开(公告)号:ES3011834T3

    公开(公告)日:2025-04-08

    申请号:ES18160825

    申请日:2018-03-08

    Applicant: INTEL CORP

    Abstract: Se describe un aparato para facilitar el procesamiento de una matriz dispersa. El aparato incluye varias unidades de procesamiento, cada una con uno o más elementos de procesamiento, incluyendo lógica para leer operandos, una unidad de multiplicación para multiplicar dos o más operandos y un programador para identificar operandos con valor cero e impedir su programación en la unidad de multiplicación. (Traducción automática con Google Translate, sin valor legal)

    9.
    发明专利
    未知

    公开(公告)号:AT549680T

    公开(公告)日:2012-03-15

    申请号:AT07784526

    申请日:2007-06-22

    Applicant: INTEL CORP

    Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

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