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    SYSTEM AND METHOD FOR PROVIDING RELIABLE TRANSMISSION IN A BUFFERED MEMORY SYSTEM
    1.
    发明申请
    SYSTEM AND METHOD FOR PROVIDING RELIABLE TRANSMISSION IN A BUFFERED MEMORY SYSTEM 审中-公开
    用于在缓冲存储器系统中提供可靠传输的系统和方法

    公开(公告)号：WO0223352A3

    公开(公告)日：2002-08-15

    申请号：PCT/US0128930

    申请日：2001-09-14

    Applicant: INTEL CORP ,  HALBERT JOHN ,  WILLIAMS MICHAEL ,  BONELLA RANDY ,  DODD JAMES

    Inventor： HALBERT JOHN ,  WILLIAMS MICHAEL ,  BONELLA RANDY ,  DODD JAMES

    IPC: G06F13/42 ,  G11C5/00 ,  G11C7/22

    CPC classification number: G06F13/4239

    Abstract: The present invention provides a system and method for providing reliable transmission in a buffered memory system. The system includes memory devices memory controller, data buffers, an address/command buffer, and a clock circuit. The memory controller sends data, address information, status information and command information, to the memory devices and receives data from the memory devices. The buffers interconnect the memory devices and the memory controller. The clock circuit is embedded in the addr/cmd buffer. The clock circuit takes and input clock and outputs an output clock to the data buffers and/or the memory devices to control clock-shew to the data buffers and/or the memory devices.

    Abstract translation: 本发明提供了一种用于在缓冲存储器系统中提供可靠传输的系统和方法。 该系统包括存储器件存储器控制器，数据缓冲器，地址/命令缓冲器和时钟电路。 存储器控制器向存储器件发送数据，地址信息，状态信息和命令信息，并从存储器件接收数据。 缓冲器互连存储器件和存储器控制器。 时钟电路嵌入在addr / cmd缓冲区中。 时钟电路接收并输入时钟，并将输出时钟输出到数据缓冲器和/或存储器件，以控制数据缓冲器和/或存储器件的时钟频率。

    APPARATUS FOR IMPLEMENTING A BUFFERED DAISY-CHAIN RING CONNECTION BETWEEN A MEMORY CONTROLLER AND MEMORY MODULES
    2.
    发明申请
    APPARATUS FOR IMPLEMENTING A BUFFERED DAISY-CHAIN RING CONNECTION BETWEEN A MEMORY CONTROLLER AND MEMORY MODULES 审中-公开
    用于在存储器控制器和存储器模块之间实现缓冲的数据链连接的装置

    公开(公告)号：WO0223353A3

    公开(公告)日：2003-07-31

    申请号：PCT/US0129236

    申请日：2001-09-18

    Applicant: INTEL CORP ,  HALBERT JOHN ,  BONELLA RANDY ,  LAM CHUNG ,  DODD JAMES

    Inventor： HALBERT JOHN ,  BONELLA RANDY ,  LAM CHUNG ,  DODD JAMES

    IPC: G06F13/16 ,  G06F13/42 ,  G11C5/00

    CPC classification number: G06F13/1684 ,  G06F13/4256 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A plurality of memory modules interface through a daisy-chain providing a point-to-point connection for each memory module. The first and last memory module in the daisy chain each connect to a separate memory controller port forming a ring circuit. A distinct set of signals connect the memory modules in each direction. A junction circuit in each memory module provides line isolation, a coupling to the adjoining memory modules in the daisy chain, or in the case of the first and last memory module in the daisy chain, a memory module and a memory controller, and a data synchronization circuit. Each junction circuit provides as well as voltage conversion so that the memory devices on a memory module operate at a different voltage than the memory controller, and multiplexing/de-mulitplexing so that a lesser number of lines interfaces with each junction circuit.

    Abstract translation: 多个存储器模块通过菊花链接口，为每个存储器模块提供点对点连接。 菊花链中的第一个和最后一个存储器模块都连接到形成环形电路的单独的存储器控​​制器端口。 一组独特的信号在每个方向连接存储器模块。 每个存储器模块中的结电路提供线路隔离，耦合到菊花链中的相邻存储器模块，或者在菊花链中的第一和最后存储器模块的情况下，存储器模块和存储器控制器以及数据 同步电路 每个结电路提供以及电压转换，使得存储器模块上的存储器件在与存储器控制器不同的电压下工作，并且复用/解复用，使得较少数量的线路与每个结电路接口。

    COMMON MEMORY DEVICE FOR VARIABLE DEVICE WIDTH AND SCALABLE PRE-FETCH AND PAGE SIZE
    3.
    发明申请
    COMMON MEMORY DEVICE FOR VARIABLE DEVICE WIDTH AND SCALABLE PRE-FETCH AND PAGE SIZE 审中-公开
    用于可变器件宽度和可扩展前置电流和页面大小的通用存储器件

    公开(公告)号：WO2010039625A3

    公开(公告)日：2010-07-01

    申请号：PCT/US2009058531

    申请日：2009-09-28

    Applicant: INTEL CORP ,  BAINS KULJIT S ,  HALBERT JOHN

    Inventor： BAINS KULJIT S ,  HALBERT JOHN

    IPC: G11C11/4093 ,  G11C7/00 ,  G11C11/4063 ,  G11C11/4096

    CPC classification number: G11C8/12 ,  G11C7/1021 ,  G11C7/1045 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/108

    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a x4 mode, a x8 mode, and a x16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.

    Abstract translation: 本发明的实施例通常涉及用于可变设备宽度和可缩放预取和页面大小的公共存储器设备的系统，方法和设备。 在一些实施例中，公共存储器件（例如DRAM）可以以包括例如x4模式，x8模式和x16模式在内的多种模式中的任何一种工作。 由DRAM提供的页面大小可以根据DRAM的模式而变化。 在一些实施例中，由DRAM预取的数据量也根据DRAM的模式而变化。

    BUFFERED MEMORY MODULE WITH IMPLICIT TO EXPLICIT MEMORY COMMAND EXPANSION
    7.
    发明申请
    BUFFERED MEMORY MODULE WITH IMPLICIT TO EXPLICIT MEMORY COMMAND EXPANSION 审中-公开
    缓冲存储器模块，不明显的存储器命令扩展

    公开(公告)号：WO2005050599A3

    公开(公告)日：2006-04-20

    申请号：PCT/US2004036964

    申请日：2004-11-05

    Applicant: INTEL CORP ,  HALBERT JOHN ,  FREEMAN CHRIS ,  WILLIAMS MICHAEL ,  BAINS KILJIT ,  ELLIS ROBERT ,  VOGT PETE

    Inventor： HALBERT JOHN ,  FREEMAN CHRIS ,  WILLIAMS MICHAEL ,  BAINS KILJIT ,  ELLIS ROBERT ,  VOGT PETE

    IPC: G06F13/16

    CPC classification number: G06F13/16

    Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.

    Abstract translation: 在实施例中包括用于缓冲存储器模块的方法和装置。 在示例性系统中，存储器模块具有接收存储器命令和数据的缓冲器，然后通过单独的接口将这些命令和数据呈现给物理存储器设备。 缓冲器具有接受隐含存储器命令的功能，即，不包含完全形成的存储器件命令的命令，而是指示存储器模块缓冲器形成一个或多个完全形成的存储器件命令以执行存储器操作 。 例如，可以通过指令存储器模块清除存储器区域或将区域复制到存储器中的第二区域的命令来保存实质存储器通道带宽。 描述和要求保护其他实施例。

    MEMORY MODULE AND MEMORY COMPONENT BUILT-IN SELF TEST
    8.
    发明申请
    MEMORY MODULE AND MEMORY COMPONENT BUILT-IN SELF TEST 审中-公开
    内存模块和内存组件内置自检

    公开(公告)号：WO0225957A2

    公开(公告)日：2002-03-28

    申请号：PCT/US0128774

    申请日：2001-09-14

    Applicant: INTEL CORP ,  HALBERT JOHN ,  BONELLA RANDY

    Inventor： HALBERT JOHN ,  BONELLA RANDY

    IPC: G11C29/14 ,  H04Q1/14 ,  H04M3/22

    CPC classification number: G11C29/12015 ,  G11C11/401 ,  G11C29/14 ,  G11C2029/0405

    Abstract: A memory component with built-in self test includes a memory array. An input/output interface is coupled to the memory array and has a loopback. A controller is provided to transmit memory array test data to the memory array to store the memory array test data, and to read the memory array test data from the memory array. A compare register is also provided to compare the memory array test data transmitted to the memory array with the memory array test data read from the memory array.

    Abstract translation: 具有内置自检功能的内存组件包括一个内存阵列。 输入/输出接口耦合到存储器阵列并具有环回。 提供控制器将存储器阵列测试数据发送到存储器阵列以存储存储器阵列测试数据，并从存储器阵列读取存储器阵列测试数据。 还提供了比较寄存器，用于将发送到存储器阵列的存储器阵列测试数据与从存储器阵列读取的存储器阵列测试数据进行比较。

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