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    ERROR MANAGEMENT ACROSS HARDWARE AND SOFTWARE LAYERS
    1.
    发明申请
    ERROR MANAGEMENT ACROSS HARDWARE AND SOFTWARE LAYERS 审中-公开
    硬件和软件层之间的错误管理

    公开(公告)号：WO2012121777A3

    公开(公告)日：2012-11-08

    申请号：PCT/US2011066524

    申请日：2011-12-21

    Applicant: INTEL CORP ,  CARTER NICHOLAS P ,  HANNAH ERIC C ,  NAEIMI HELIA ,  HAYCOCK MATTHEW B ,  GARDNER DONALD S ,  BORKAR SHEKHAR Y

    Inventor： CARTER NICHOLAS P ,  HANNAH ERIC C ,  NAEIMI HELIA ,  HAYCOCK MATTHEW B ,  GARDNER DONALD S ,  BORKAR SHEKHAR Y

    IPC: G06F11/28 ,  G06F11/07 ,  G06F11/22

    CPC classification number: G06F11/0781 ,  G06F11/0772 ,  G06F11/0793 ,  G06F11/1425 ,  G06F11/1428

    Abstract: Generally, this disclosure provides error management across hardware and software layers to enable hardware and software to deliver reliable operation in the face of errors and hardware variation due to aging, manufacturing tolerances, etc. In one embodiment, an error management module is provided that gathers information from the hardware and software layers, and detects and diagnoses errors. A hardware or software recovery technique may be selected to provide efficient operation, and, in some embodiments, the hardware device may be reconfigured to prevent future errors and to permit the hardware device to operate despite a permanent error.

    Abstract translation: 通常，本公开提供跨越硬件层和软件层的错误管理，以使硬件和软件能够在由于老化，制造容差等而导致的错误和硬件变化面前提供可靠的操作。在一个实施例中，提供了错误管理模块， 来自硬件和软件层的信息，并检测和诊断错误。 可以选择硬件或软件恢复技术来提供有效的操作，并且在一些实施例中，硬件设备可以被重新配置以防止将来的错误并且允许硬件设备在尽管存在永久错误的情况下进行操作。

    Impedance control circuit
    2.
    发明专利
    Impedance control circuit 未知

    公开(公告)号：AU8495298A

    公开(公告)日：1999-02-22

    申请号：AU8495298

    申请日：1998-07-17

    Applicant: INTEL CORP

    Inventor： MOONEY STEPHEN R ,  HAYCOCK MATTHEW B ,  KENNEDY JOSEPH T

    IPC: H03K19/00 ,  H03K19/0175

    Abstract: Briefly, in accordance with one embodiment of the invention an integrated circuit includes: a digital feedback control circuit to adjust the impedance of an interface circuit output buffer based, at least in part, on having adjusted the impedance of a non-data signal output buffer coupled to an external impedance. Briefly, in accordance with another embodiment of the invention, a method of digitally adjusting the impedance of an interface circuit output buffer comprises: digitally adjusting the impedance of a non-data signal output buffer coupled to an external impedance, and digitally adjusting the impedance of the interface circuit output buffer based, at least in part, on the digitally adjusted impedance of the non-data signal output buffer.

    IMPEDANCE CONTROL CIRCUIT
    3.
    发明申请
    IMPEDANCE CONTROL CIRCUIT 审中-公开
    阻抗控制电路

    公开(公告)号：WO9906845A3

    公开(公告)日：1999-09-10

    申请号：PCT/US9814846

    申请日：1998-07-17

    Applicant: INTEL CORP ,  MOONEY STEPHEN R ,  HAYCOCK MATTHEW B ,  KENNEDY JOSEPH T

    Inventor： MOONEY STEPHEN R ,  HAYCOCK MATTHEW B ,  KENNEDY JOSEPH T

    IPC: H03K19/00 ,  H03K19/0175 ,  H03K17/16

    CPC classification number: H03K19/017545 ,  H03K19/0005

    Abstract: Briefly, in accordance with one embodiment of the invention an integrated circuit includes: a digital feedback control circuit (310, 360) to adjust the impedance of an interface circuit output buffer (320) based, at least in part, on having adjusted the impedance of a non-data signal output buffer (330) coupled to an external impedance (350, 370). Briefly, in accordance with another embodiment of the invention, a method of digitally adjusting the impedance (310) of an interface circuit output buffer (320) comprises: digitally adjusting the impedance of a non-data signal output buffer (330) coupled to an external impedance (350, 370), and digitally adjusting the impedance of the interface circuit output buffer (320) based, at least in part, on the digitally adjusted impedance of the non-data signal output buffer (330).

    Abstract translation: 简而言之，根据本发明的一个实施例，集成电路包括：数字反馈控制电路（310,360），用于至少部分地基于调整阻抗来调节接口电路输出缓冲器（320）的阻抗 耦合到外部阻抗（350,370）的非数据信号输出缓冲器（330）。 简而言之，根据本发明的另一个实施例，一种数字调节接口电路输出缓冲器（320）的阻抗（310）的方法包括：数字调节与数据信号输出缓冲器（330）耦合的非数据信号输出缓冲器 至少部分地基于非数据信号输出缓冲器（330）的数字调节的阻抗来数字地调整接口电路输出缓冲器（320）的阻抗（350,370）。

    IMPEDANCE CONTROL CIRCUIT
    4.
    发明专利
    IMPEDANCE CONTROL CIRCUIT 未知

    公开(公告)号：HK1027398A1

    公开(公告)日：2001-01-12

    申请号：HK00106494

    申请日：2000-10-12

    Applicant: INTEL CORP

    Inventor： MOONEY STEPHEN R ,  HAYCOCK MATTHEW B ,  KENNEDY JOSEPH T

    IPC: H03K19/00 ,  H03K19/0175 ,  G01R ,  H03K

    Abstract: Briefly, in accordance with one embodiment of the invention an integrated circuit includes: a digital feedback control circuit to adjust the impedance of an interface circuit output buffer based, at least in part, on having adjusted the impedance of a non-data signal output buffer coupled to an external impedance. Briefly, in accordance with another embodiment of the invention, a method of digitally adjusting the impedance of an interface circuit output buffer comprises: digitally adjusting the impedance of a non-data signal output buffer coupled to an external impedance, and digitally adjusting the impedance of the interface circuit output buffer based, at least in part, on the digitally adjusted impedance of the non-data signal output buffer.

    IMPEDANCE CONTROL CIRCUIT
    5.
    发明公开
    IMPEDANCE CONTROL CIRCUIT 失效
    IMPEDANZSTEUERUNGSSCHALTUNG

    公开(公告)号：EP1010013A4

    公开(公告)日：2000-10-18

    申请号：EP98935769

    申请日：1998-07-17

    Applicant: INTEL CORP

    Inventor： MOONEY STEPHEN R ,  HAYCOCK MATTHEW B ,  KENNEDY JOSEPH T

    IPC: H03K19/00 ,  H03K19/0175 ,  G01R3/00

    CPC classification number: H03K19/017545 ,  H03K19/0005

    Abstract: Briefly, in accordance with one embodiment of the invention an integrated circuit includes: a digital feedback control circuit to adjust the impedance of an interface circuit output buffer based, at least in part, on having adjusted the impedance of a non-data signal output buffer coupled to an external impedance. Briefly, in accordance with another embodiment of the invention, a method of digitally adjusting the impedance of an interface circuit output buffer comprises: digitally adjusting the impedance of a non-data signal output buffer coupled to an external impedance, and digitally adjusting the impedance of the interface circuit output buffer based, at least in part, on the digitally adjusted impedance of the non-data signal output buffer.

    Abstract translation: 简言之，根据本发明的一个实施例，一种集成电路包括：数字反馈控制电路，用于至少部分地基于调整了非数据信号输出缓冲器的阻抗来调整接口电路输出缓冲器的阻抗 耦合到一个外部阻抗。 简而言之，根据本发明的另一个实施例，一种数字调节接口电路输出缓冲器的阻抗的方法包括：数字调节耦合到外部阻抗的非数据信号输出缓冲器的阻抗，并且数字调节 接口电路输出缓冲器至少部分地基于非数据信号输出缓冲器的数字调整的阻抗。

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