公开(公告)号：JP2012216784A

公开(公告)日：2012-11-08

申请号：JP2012053192

申请日：2012-03-09

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： NICHOLAS P COWLEY ,  ISAAC ALI ,  STEPHEN J SPINKS

IPC: H01F19/00 ,  H01F17/02 ,  H01F37/00 ,  H02M3/155

CPC classification number: H02M3/1584 ,  H01F17/02 ,  Y10T29/49071

Abstract: PROBLEM TO BE SOLVED: To provide an efficient inductor component to facilitate integration of switched mode buck voltage regulators into system-on-chips (SOCs).SOLUTION: At least two counter wound aircoils are formed on a surface mounted device (SMD) inductor former. The aircoils are connected to three terminals on the SMD former. A single terminal is connected to a common node of both windings with two independent terminals accessing the other winding node.

Abstract translation: 要解决的问题：提供有效的电感器部件，以便于将开关式降压稳压器集成到片上系统（SOC）中。

解决方案：在表面安装器件（SMD）电感器形成器上形成至少两个计数器缠绕的电极。 电磁线圈连接到SMD前体上的三个端子。 单个端子连接到两个绕组的公共节点，两个独立端子接入另一个绕组节点。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：GB2427086B

公开(公告)日：2007-04-25

申请号：GB0610631

申请日：2006-05-31

Applicant: INTEL CORP

Inventor： ISAAC ALI ,  COWLEY NICHOLAS PAUL ,  SAWYER DAVID ALBERT

IPC: H03L7/081 ,  H03D7/16

Abstract: A variable signal delaying circuit comprising an analog delay line having a control input for controlling the variable delay. A phase detector compares the input and output signals of the delaying circuit and supplies an output signal to a charge pump and integrator. A pulse stream generating arrangement produces pulse streams of different pulse widths and pulse control logic controls a selector for selecting any one of the pulse streams. In a first mode of operation, the control logic monitors the charge pump/filter output and selects the pulse stream which minimizes change in the output. The selection is fixed and the output of the charge pump/filter is then supplied as a correction signal to the control input of the analog delay line. Such an arrangement may be used to maintain minimum phase imbalance in I and Q signal paths of a quadrature frequency converter.

公开(公告)号：GB2434045A

公开(公告)日：2007-07-11

申请号：GB0614231

申请日：2006-07-18

Applicant: INTEL CORP

Inventor： ISAAC ALI ,  COWLEY NICHOLAS PAUL

IPC: H03D7/16 ,  H03K5/15 ,  H03K23/54 ,  H04B1/26

Abstract: A frequency changer is provided for a radio frequency tuner. The frequency changer comprises a mixer 3 comprising a plurality of mixing stages 10a, 11a; 10b, 11b; 10c, 11c. Individual waveforms LO1, LO2 and LO3 are supplied to respective mixing stages 11a, 11b, 11c from local oscillator. The waveforms are of the same frequency but of different phases. Each mixing stage performs frequency conversion of the input frequency signal with its respective commutating signal and the frequency changed outputs of the mixing stages 11a, 11b, 11c are summed 22, 23 to form the output 21 of the mixer. The output signals of these mixing stages are supplied without relative phase shift to the summer. Improved harmonic mixing performance is achieved without degradation of the noise and intermodulation performance of the mixer.

公开(公告)号：GB2427086A

公开(公告)日：2006-12-13

申请号：GB0610631

申请日：2006-05-31

Applicant: INTEL CORP

Inventor： ISAAC ALI ,  COWLEY NICHOLAS PAUL ,  SAWYER DAVID ALBERT

IPC: H03L7/081 ,  H03D7/16

Abstract: A variable signal delaying circuit comprises an analog delay line (21, 23) having a control input (27) for controlling the variable delay. A phase detector (32, 34) compares the input and output signals of the delaying circuit and supplies an output signal to a charge pump and integrator (33, 35). A pulse stream generating arrangement (39-41) produces pulse streams of different pulse widths and pulse control logic (31) controls a selector (38) for selecting any one of the pulse streams. In a first mode of operation, the control logic (31) monitors the charge pump/filter output and selects the pulse stream which minimises change in the output. The selection is fixed and the output of the charge pump/filter (33, 35) is then supplied as a correction signal to the control input (27) of the analog delay line (21, 23). Such an arrangement may be used to maintain minimum phase imbalance in I and Q signal paths of a quadrature frequency converter (12-17, 21-23).