公开(公告)号：JP2008104157A

公开(公告)日：2008-05-01

申请号：JP2007216703

申请日：2007-08-23

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： COWLEY NICK ,  SAWYER DAVID ALBERT ,  ALI ISAAC

IPC: H04B1/26 ,  H04L27/22 ,  H04L27/38

CPC classification number: H03D3/007

Abstract: PROBLEM TO BE SOLVED: To provide a multi-standard tuner capable of semiconductor integration. SOLUTION: A zero intermediate frequency (ZIF) conversion technique may be combined with digitally-controlled selectivity filtering and digital signal processor (DSP)-based signal impairment processing, to yield multi-standard tuner capable of semiconductor integration. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供能够进行半导体集成的多标准调谐器。 解决方案：零中频（ZIF）转换技术可以与数字控制的选择性滤波和基于数字信号处理器（DSP）的信号损伤处理相结合，以产生能够进行半导体集成的多标准调谐器。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007060669A

公开(公告)日：2007-03-08

申请号：JP2006226457

申请日：2006-08-23

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： SAWYER DAVID ALBERT ,  COWLEY NICHOLAS PAUL ,  ALI ISAAC

IPC: H03K5/13 ,  G11B20/10 ,  H03K5/00 ,  H03K5/04 ,  H03K5/135 ,  H03K5/15 ,  H03K5/156 ,  H03L7/081 ,  H03L7/18 ,  H04B1/26

CPC classification number: H03K5/135 ,  H03K5/133 ,  H03K5/15 ,  H03K5/1565 ,  H03K2005/00286 ,  H03L7/18

Abstract: PROBLEM TO BE SOLVED: To provide a pulse generator capable of enhancing phase balancing or the like of a frequency converter. SOLUTION: The pulse generator comprises an oscillator 3 and a selecting arrangement for selecting how many of a first group 13 of delay elements are connected in series for delaying an IF clock of the pulse generator. Identical delay elements 26 receiving the IF clock in inputs are connected in series to form a second group. A measuring circuit 27 repeatedly measures the delay provided by the second group, for example providing output pulses IP whose pulse width IPD is equal to the delay. Reference pulse generators 29, 30 generate a series of reference pulses RP, each of which has a duration equal with a fraction of the IF clock period. A charge pump/integrator 28 compares the measurement and reference pulses to generate an error signal that is fed back to timing delay control inputs of all the delay elements such that the widths of the measurement and reference pulses are made equal to each other. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供能够增强变频器的相位平衡等的脉冲发生器。 解决方案：脉冲发生器包括振荡器3和选择装置，用于选择延迟元件的第一组13中有多少串联连接以延迟脉冲发生器的IF时钟。 在输入中接收IF时钟的相同延迟元件26串联连接以形成第二组。 测量电路27重复测量由第二组提供的延迟，例如提供脉冲宽度IPD等于延迟的输出脉冲IP。 参考脉冲发生器29,30产生一系列参考脉冲RP，每个参考脉冲具有等于IF时钟周期的一部分的持续时间。 电荷泵/积分器28比较测量和参考脉冲以产生反馈到所有延迟元件的定时延迟控制输入的误差信号，使得测量和参考脉冲的宽度彼此相等。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：GB2427086B

公开(公告)日：2007-04-25

申请号：GB0610631

申请日：2006-05-31

Applicant: INTEL CORP

Inventor： ISAAC ALI ,  COWLEY NICHOLAS PAUL ,  SAWYER DAVID ALBERT

IPC: H03L7/081 ,  H03D7/16

Abstract: A variable signal delaying circuit comprising an analog delay line having a control input for controlling the variable delay. A phase detector compares the input and output signals of the delaying circuit and supplies an output signal to a charge pump and integrator. A pulse stream generating arrangement produces pulse streams of different pulse widths and pulse control logic controls a selector for selecting any one of the pulse streams. In a first mode of operation, the control logic monitors the charge pump/filter output and selects the pulse stream which minimizes change in the output. The selection is fixed and the output of the charge pump/filter is then supplied as a correction signal to the control input of the analog delay line. Such an arrangement may be used to maintain minimum phase imbalance in I and Q signal paths of a quadrature frequency converter.

公开(公告)号：AT386366T

公开(公告)日：2008-03-15

申请号：AT06118441

申请日：2006-08-04

Applicant: INTEL CORP

Inventor： SAWYER DAVID ALBERT ,  COWLEY NICHOLAS PAUL ,  ALI ISAAC

IPC: H03K5/13 ,  H03K5/00 ,  H03K5/135 ,  H03K5/15 ,  H03K5/156 ,  H03L7/081 ,  H03L7/18

Abstract: A pulse generator is provided for generating pulses with a selectable variable width and/or delay. The pulse generator comprises an oscillator (3) and a selecting arrangement for selecting how many of a first group (13) of delay elements are connected in series for delaying the oscillator signal (IF clock). Identical delay elements (26) are connected in series to form a second group, whose input receives the oscillator signal (IF clock). A measuring circuit (27) repeatedly measures the delay provided by the second group, for example providing output pulses (IP) whose width or duration (IPD) is equal to the delay. A reference pulse generator (29,30) generates a series of reference pulses (RP), each of which is of a predetermined duration equal to a fraction of the oscillator signal (IF clock) period. A control circuit, such as a charge pump and integrator (28), compares the measurement pulses (IP) and the reference pulses (RP) to generate an error signal which is fed back to timing delay control inputs of all of the delay elements such that the widths of the measurement and reference pulses (IP,RP) are made substantially equal to each other.

公开(公告)号：DE602006000532T2

公开(公告)日：2009-02-19

申请号：DE602006000532

申请日：2006-08-04

Applicant: INTEL CORP

Inventor： SAWYER DAVID ALBERT ,  COWLEY NICHOLAS PAUL ,  ALI ISAAC

IPC: H03K5/13 ,  H03K5/00 ,  H03K5/135 ,  H03K5/15 ,  H03K5/156 ,  H03L7/081 ,  H03L7/18

Abstract: A pulse generator is provided for generating pulses with a selectable variable width and/or delay. The pulse generator comprises an oscillator (3) and a selecting arrangement for selecting how many of a first group (13) of delay elements are connected in series for delaying the oscillator signal (IF clock). Identical delay elements (26) are connected in series to form a second group, whose input receives the oscillator signal (IF clock). A measuring circuit (27) repeatedly measures the delay provided by the second group, for example providing output pulses (IP) whose width or duration (IPD) is equal to the delay. A reference pulse generator (29,30) generates a series of reference pulses (RP), each of which is of a predetermined duration equal to a fraction of the oscillator signal (IF clock) period. A control circuit, such as a charge pump and integrator (28), compares the measurement pulses (IP) and the reference pulses (RP) to generate an error signal which is fed back to timing delay control inputs of all of the delay elements such that the widths of the measurement and reference pulses (IP,RP) are made substantially equal to each other.

公开(公告)号：DE602006000532D1

公开(公告)日：2008-03-27

申请号：DE602006000532

申请日：2006-08-04

Applicant: INTEL CORP

Inventor： SAWYER DAVID ALBERT ,  COWLEY NICHOLAS PAUL ,  ALI ISAAC

IPC: H03K5/13 ,  H03K5/00 ,  H03K5/135 ,  H03K5/15 ,  H03K5/156 ,  H03L7/081 ,  H03L7/18

Abstract: A pulse generator is provided for generating pulses with a selectable variable width and/or delay. The pulse generator comprises an oscillator (3) and a selecting arrangement for selecting how many of a first group (13) of delay elements are connected in series for delaying the oscillator signal (IF clock). Identical delay elements (26) are connected in series to form a second group, whose input receives the oscillator signal (IF clock). A measuring circuit (27) repeatedly measures the delay provided by the second group, for example providing output pulses (IP) whose width or duration (IPD) is equal to the delay. A reference pulse generator (29,30) generates a series of reference pulses (RP), each of which is of a predetermined duration equal to a fraction of the oscillator signal (IF clock) period. A control circuit, such as a charge pump and integrator (28), compares the measurement pulses (IP) and the reference pulses (RP) to generate an error signal which is fed back to timing delay control inputs of all of the delay elements such that the widths of the measurement and reference pulses (IP,RP) are made substantially equal to each other.

公开(公告)号：GB2427086A

公开(公告)日：2006-12-13

申请号：GB0610631

申请日：2006-05-31

Applicant: INTEL CORP

Inventor： ISAAC ALI ,  COWLEY NICHOLAS PAUL ,  SAWYER DAVID ALBERT

IPC: H03L7/081 ,  H03D7/16

Abstract: A variable signal delaying circuit comprises an analog delay line (21, 23) having a control input (27) for controlling the variable delay. A phase detector (32, 34) compares the input and output signals of the delaying circuit and supplies an output signal to a charge pump and integrator (33, 35). A pulse stream generating arrangement (39-41) produces pulse streams of different pulse widths and pulse control logic (31) controls a selector (38) for selecting any one of the pulse streams. In a first mode of operation, the control logic (31) monitors the charge pump/filter output and selects the pulse stream which minimises change in the output. The selection is fixed and the output of the charge pump/filter (33, 35) is then supplied as a correction signal to the control input (27) of the analog delay line (21, 23). Such an arrangement may be used to maintain minimum phase imbalance in I and Q signal paths of a quadrature frequency converter (12-17, 21-23).