公开(公告)号：DE69530788D1

公开(公告)日：2003-06-18

申请号：DE69530788

申请日：1995-12-06

Applicant: INTEL CORP

Inventor： KARDACH JAMES ,  CHO SOO ,  PETERSON B ,  LANE R ,  JOSHI M ,  SONGER NEIL

IPC: G06F13/24 ,  G06F9/46 ,  G06F13/14

Abstract: A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.

公开(公告)号：DE69530788T2

公开(公告)日：2004-03-18

申请号：DE69530788

申请日：1995-12-06

Applicant: INTEL CORP

Inventor： KARDACH JAMES ,  CHO SOO ,  PETERSON B ,  LANE R ,  JOSHI M ,  SONGER NEIL

IPC: G06F13/24 ,  G06F9/46 ,  G06F13/14

Abstract: A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.