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    Downstream device service latency reporting for power management
    1.
    发明专利
    Downstream device service latency reporting for power management 有权
    下游设备服务延迟报告用于电源管理

    公开(公告)号：JP2010165350A

    公开(公告)日：2010-07-29

    申请号：JP2009293551

    申请日：2009-12-24

    Applicant: Intel Corp ,  インテル・コーポレーション

    Inventor： JEYASEELAN JAYA ,  WALSH JIM ,  GOUGH ROBERT ,  COOPER BARNES ,  SONGER NEIL

    IPC: G06F1/32 ,  G06F1/26 ,  G06F1/28

    CPC classification number: H04W52/0225 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3296 ,  G06F13/4282 ,  H04L43/0858 ,  Y02B60/50 ,  Y02D10/151 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/23

    Abstract: PROBLEM TO BE SOLVED: To enable an extend operation by power management of battery-powered mobile devices and systems.
    SOLUTION: By a personal computer, a transition from a first state to a second state for at least a part of a downstream device can be identified. First and second states may correspond to different levels relating to activity for at least a part of the downstream device. Data corresponding to a service latency can be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency.
    COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：通过电池供电的移动设备和系统的电源管理实现扩展操作。 解决方案：通过个人计算机，可以识别对于下游设备的至少一部分从第一状态向第二状态的转变。 第一和第二状态可以对应于与下游设备的至少一部分的活动有关的不同级别。 响应于至少部分地基于服务等待时间的一个或多个上游设备的所识别的转换来管理电力，可以将对应于服务等待时间的数据发送到上游设备。 版权所有（C）2010，JPO＆INPIT

    Method and apparatus for caching system management mode information with other information
    2.
    发明专利
    Method and apparatus for caching system management mode information with other information 未知

    公开(公告)号：AU3297597A

    公开(公告)日：1998-01-05

    申请号：AU3297597

    申请日：1997-05-27

    Applicant: INTEL CORP

    Inventor： REINHARDT DENNIS ,  KARDACH JAMES P ,  HORIGAN JOHN W ,  SONGER NEIL ,  GLEW ANDREW F

    IPC: G06F9/48 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G06F12/14 ,  G06F9/30 ,  G06F9/22 ,  G06F12/10

    Abstract: A novel method and apparatus to cache System Management Mode (SMM) data with other data to improve performance and reduce latency of SMM handler routines. This method and apparatus allows SMM data and non-SMM data to be distinguished in the cache without requiring extra cache bits which can add to the cost of implementation. Since SMM data and non-SMM data can coexist in the cache, there is no need for time consuming cache flush cycles when switching between the two modes. Since SMM data can be cached, performance of SMM routines are improved. This method and apparatus defines the SMRAM address range to be a range of addresses representable by the tag, but not directly corresponding to installed main memory. When accesses are made to SMRAM addresses, they are redirected to an unused portion of main memory. Protection mechanisms may be implemented to limit access to these SMRAM addresses when not in SMM.

    SERIAL INTERRUPT BUS PROTOCOL
    4.
    发明公开
    SERIAL INTERRUPT BUS PROTOCOL 失效
    串行中断总线协议

    公开(公告)号：EP0796464A4

    公开(公告)日：1999-07-28

    申请号：EP95943003

    申请日：1995-12-06

    Applicant: INTEL CORP

    Inventor： KARDACH JAMES ,  CHO SUNG SOO ,  PETERSON NICHOLAS B ,  LANE THOMAS R ,  JOSHI JAYESH M ,  SONGER NEIL

    IPC: G06F13/24 ,  G06F9/46 ,  G06F13/14

    CPC classification number: G06F13/24

    Abstract: A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller (22) without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller (25) which follows the same state machine logic as the sytem peripherals. When the serial interrupt controller (25) receives an active signal, it determines which interrupt signal to provide to the system's interrupt controller (22) based on the interrupt state of the interrupt controller state machine logic. Peripherals (41, 42) on a secondary serial interrupt bus may be daisy chained with peripherals (30, 31, 32) on a primary system interrupt bus through a system interrupt bridge (40) which also includes state machine logic for following the same state diagram as the system peripherals.

    7.
    发明专利
    未知

    公开(公告)号：DE69732181D1

    公开(公告)日：2005-02-10

    申请号：DE69732181

    申请日：1997-05-27

    Applicant: INTEL CORP

    Inventor： REINHARDT DENNIS ,  KARDACH P ,  HORIGAN W ,  SONGER NEIL ,  GLEW F

    IPC: G06F9/48 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G06F12/14 ,  G06F9/30 ,  G06F9/22 ,  G06F12/10 ,  G06F9/46

    Abstract: A novel method and apparatus to cache System Management Mode (SMM) data with other data to improve performance and reduce latency of SMM handler routines. This method and apparatus allows SMM data and non-SMM data to be distinguished in the cache without requiring extra cache bits which can add to the cost of implementation. Since SMM data and non-SMM data can coexist in the cache, there is no need for time consuming cache flush cycles when switching between the two modes. Since SMM data can be cached, performance of SMM routines are improved. This method and apparatus defines the SMRAM address range to be a range of addresses representable by the tag, but not directly corresponding to installed main memory. When accesses are made to SMRAM addresses, they are redirected to an unused portion of main memory. Protection mechanisms may be implemented to limit access to these SMRAM addresses when not in SMM.

    8.
    发明专利
    未知

    公开(公告)号：DE69530788T2

    公开(公告)日：2004-03-18

    申请号：DE69530788

    申请日：1995-12-06

    Applicant: INTEL CORP

    Inventor： KARDACH JAMES ,  CHO SOO ,  PETERSON B ,  LANE R ,  JOSHI M ,  SONGER NEIL

    IPC: G06F13/24 ,  G06F9/46 ,  G06F13/14

    Abstract: A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.

    Berichten der Dienstlatenzzeit eines Downstream-Gerätes für Power Management
    9.
    发明专利
    Berichten der Dienstlatenzzeit eines Downstream-Gerätes für Power Management 未知

    公开(公告)号：DE102009060269A1

    公开(公告)日：2010-07-01

    申请号：DE102009060269

    申请日：2009-12-23

    Applicant: INTEL CORP

    Inventor： JEYASEELAN JAYA ,  WALSH JIM ,  GOUGH ROBERT ,  COOPER BARNES ,  SONGER NEIL

    IPC: G06F1/32 ,  G06F13/00 ,  G06F13/38

    Abstract: Bei einer offenbarten Ausführungsform kann ein Übergang von einem ersten Zustand in einen zweiten, unterschiedlichen Zustand für zumindest einen Teil eines Downstream-Gerätes identifiziert werden. Die ersten und zweiten Zustände können verschiedene Leveln entsprechen, die die Aktivität für zumindest einen Teil des Downstream-Gerätes betreffen. Daten, die einer Dienstlatenzzeit entsprechen, können in Antwort auf den identifizierten Übergang für ein oder mehr Upstream-Geräte an ein Upstream-Gerät übertragen werden, um Energie zumindest teilweise basierend auf der Dienstlatenzzeit zu regeln. Weitere Ausführungsformen werden ebenfalls offenbart.

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