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公开(公告)号：WO0039535A9
公开(公告)日：2001-07-12
申请号：PCT/US9930350
申请日：1999-12-10
Applicant: INTEL CORP , KYNETT VIRGIL NILES , WELLS STEVEN E
Inventor： KYNETT VIRGIL NILES , WELLS STEVEN E
IPC: G01D18/00
CPC classification number: G01D18/008
Abstract: A method for calibrating analog sensor measurements within a computer system is disclosed. The method includes the steps of generating an analog sensor measurement result, reading at least two values that define a curve from a memory device, and calculating a calibrated result using the analog sensor measurement result and the values that define the curve.
Abstract translation: 公开了一种在计算机系统内校准模拟传感器测量的方法。 该方法包括以下步骤：产生模拟传感器测量结果，读取从存储器件定义曲线的至少两个值，以及使用模拟传感器测量结果和限定曲线的值来计算校准结果。
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公开(公告)号：DE3900798A1
公开(公告)日：1989-08-31
申请号：DE3900798
申请日：1989-01-13
Applicant: INTEL CORP
Inventor： KREIFELS JERRY A , BAKER ALAN , HOEKSTRA GEORGE , KYNETT VIRGIL NILES , WELLS STEVEN , WINSTON MARK
Abstract: A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.
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公开(公告)号：BR9916679A
公开(公告)日：2001-10-16
申请号：BR9916679
申请日：1999-12-10
Applicant: INTEL CORP
Inventor： KYNETT VIRGIL NILES , WELLS STEVEN E
IPC: G01D18/00
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公开(公告)号：FR2627315B1
公开(公告)日：1993-04-30
申请号：FR8815691
申请日：1988-11-30
Applicant: INTEL CORP
Inventor： KREIFELS JERRY A , BAKER ALAN , HOEKSTRA GEORGE , KYNETT VIRGIL NILES , WELLS STEVEN , WINSTON MARK
Abstract: A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.
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公开(公告)号：DE3900979C2
公开(公告)日：2003-03-27
申请号：DE3900979
申请日：1989-01-14
Applicant: INTEL CORP
Inventor： KREIFELS JERRY A , BAKER ALAN , HOEKSTRA GEORGE , KYNETT VIRGIL NILES , WELLS STEVEN , WINSTON MARK
Abstract: PURPOSE: To program a flash memory device via a data port and to enable an erasing command port architecture by incorporating a circuit means into the same semiconductor chip as a memory executing erasing, programing and erasing/programming test in a circuit. CONSTITUTION: A data bus 20 is connected to an input/output buffer 21, and data to be inputted into a memory array 11 is connected from the bus 23a via a data latch 22. On the contrary, data to be outputted to the data bas 20 from the memory array 11 are connected to an I/O buffer 21 from a bus 23b via a sense circuit 101, thereafter data are outputted to the data 20. Input data are also connected to a command port controller 30 via the bus 23a. External signals WE and CE are further received with the command port controller 30, and control signals are fed to an address latch 13, the data latch 22, an eraser voltage generator 24, a program voltage generator 25 and an erasing/ programming test generator 26. External signals CE and DE are connected to a chip/output enable logic circuit 27.
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Patent Agency Ranking
公开(公告)号：FR2627316A1
公开(公告)日：1989-08-18
申请号：FR8815692
申请日：1988-11-30
Applicant: INTEL CORP
Inventor： KREIFELS JERRY A , BAKER ALAN , HOEKSTRA GEORGE , KYNETT VIRGIL NILES , WELLS STEVEN , WINSTON MARK
Abstract: PURPOSE: To program a flash memory device via a data port and to enable an erasing command port architecture by incorporating a circuit means into the same semiconductor chip as a memory executing erasing, programing and erasing/programming test in a circuit. CONSTITUTION: A data bus 20 is connected to an input/output buffer 21, and data to be inputted into a memory array 11 is connected from the bus 23a via a data latch 22. On the contrary, data to be outputted to the data bas 20 from the memory array 11 are connected to an I/O buffer 21 from a bus 23b via a sense circuit 101, thereafter data are outputted to the data 20. Input data are also connected to a command port controller 30 via the bus 23a. External signals WE and CE are further received with the command port controller 30, and control signals are fed to an address latch 13, the data latch 22, an eraser voltage generator 24, a program voltage generator 25 and an erasing/ programming test generator 26. External signals CE and DE are connected to a chip/output enable logic circuit 27.
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公开(公告)号：FR2627315A1
公开(公告)日：1989-08-18
申请号：FR8815691
申请日：1988-11-30
Applicant: INTEL CORP
Inventor： KREIFELS JERRY A , BAKER ALAN , HOEKSTRA GEORGE , KYNETT VIRGIL NILES , WELLS STEVEN , WINSTON MARK
Abstract: A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.
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公开(公告)号：DE3900798C2
公开(公告)日：1995-05-24
申请号：DE3900798
申请日：1989-01-13
Applicant: INTEL CORP
Inventor： KREIFELS JERRY A , BAKER ALAN , HOEKSTRA GEORGE , KYNETT VIRGIL NILES , WELLS STEVEN , WINSTON MARK
Abstract: A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.
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公开(公告)号：GB2215155B
公开(公告)日：1992-07-22
申请号：GB8819579
申请日：1988-08-17
Applicant: INTEL CORP
Inventor： KREIFELS JERRY A , BAKER ALAN , HOEKSTRA GEORGE , KYNETT VIRGIL NILES , WELLS STEVEN , WINSTON MARK
Abstract: A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.
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公开(公告)号：GB2215155A
公开(公告)日：1989-09-13
申请号：GB8819579
申请日：1988-08-17
Applicant: INTEL CORP
Inventor： KREIFELS JERRY A , BAKER ALAN , HOEKSTRA GEORGE , KYNETT VIRGIL NILES , WELLS STEVEN , WINSTON MARK
Abstract: A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.
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