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公开(公告)号：FR2627315B1
公开(公告)日：1993-04-30
申请号：FR8815691
申请日：1988-11-30
Applicant: INTEL CORP
Inventor： KREIFELS JERRY A , BAKER ALAN , HOEKSTRA GEORGE , KYNETT VIRGIL NILES , WELLS STEVEN , WINSTON MARK
Abstract: A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.
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公开(公告)号：WO2009158183A3
公开(公告)日：2010-02-25
申请号：PCT/US2009046731
申请日：2009-06-09
Applicant: INTEL CORP , TETRICK R SCOTT , JUENEMANN DALE , HOWES JORDAN , MATTHEWS JEANNA , WELLS STEVEN , HINTON GLENN , PINTO OSCAR
Inventor： TETRICK R SCOTT , JUENEMANN DALE , HOWES JORDAN , MATTHEWS JEANNA , WELLS STEVEN , HINTON GLENN , PINTO OSCAR
CPC classification number: G06F12/0868 , G06F12/0888 , G06F2212/222 , Y02D10/13
Abstract: In some embodiments, an electronic system may include a cache located between a mass storage and a system memory, and code stored on the electronic system to prevent storage of stream data in the cache and to send the stream data directly between the system memory and the mass storage based on a comparison of first metadata of a first request for first information and pre-boot stream information stored in a previous boot context. Other embodiments are disclosed and claimed.
Abstract translation: 在一些实施例中，电子系统可以包括位于大容量存储器和系统存储器之间的高速缓存器，以及存储在电子系统上的代码，以防止流数据在高速缓存中的存储并且直接在系统存储器和 基于对第一信息的第一请求的第一元数据和先前引导上下文中存储的预引导流信息的比较的大容量存储。 公开和要求保护其他实施例。
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3.发明公开
公开(公告)号：EP0813711A1
公开(公告)日：1997-12-29
申请号：EP95944199
申请日：1995-12-21
Applicant: INTEL CORP
Inventor： CHRISTOPHERSON MARK , WELLS STEVEN , ATWOOD GREG , BAUER MARK , FAZIO ALBERT , HASBUN ROBERT
CPC classification number: G11C29/765 , G06F11/1036 , G06F11/106 , G06F11/1068 , G06F11/1072 , G06F2201/88 , G11C11/5621 , G11C29/00
Abstract: A method of utilizing error detecting and correcting circuitry (56) to detect and correct errors which can occur in data stored in multi-bit cell format in a flash EEPROM memory array (23) before those errors can affect the accuracy of data provided by a flash EEPROM memory array.
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4.发明公开
公开(公告)号：EP0813711A4
公开(公告)日：1998-04-01
申请号：EP95944199
申请日：1995-12-21
Applicant: INTEL CORP
Inventor： CHRISTOPHERSON MARK , WELLS STEVEN , ATWOOD GREG , BAUER MARK , FAZIO ALBERT , HASBUN ROBERT
CPC classification number: G11C29/765 , G06F11/1036 , G06F11/106 , G06F11/1068 , G06F11/1072 , G06F2201/88 , G11C11/5621 , G11C29/00
Abstract: A method of utilizing error detecting and correcting circuitry (56) to detect and correct errors which can occur in data stored in multi-bit cell format in a flash EEPROM memory array (23) before those errors can affect the accuracy of data provided by a flash EEPROM memory array.
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公开(公告)号：DE112009000418T5
公开(公告)日：2011-04-21
申请号：DE112009000418
申请日：2009-06-09
Applicant: INTEL CORP
Inventor： TETRICK SCOTT R , JUENEMANN DALE , HOWES JORDAN , MATTHEWS JEANNA , WELLS STEVEN , HINTON GLENN , PINTO OSCAR
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Patent Agency Ranking
公开(公告)号：DE69526123D1
公开(公告)日：2002-05-02
申请号：DE69526123
申请日：1995-12-21
Applicant: INTEL CORP
Inventor： CHRISTOPHERSON MARK , WELLS STEVEN , ATWOOD GREG , BAUER MARK , FAZIO ALBERT , HASBUN ROBERT
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公开(公告)号：DE3900798A1
公开(公告)日：1989-08-31
申请号：DE3900798
申请日：1989-01-13
Applicant: INTEL CORP
Inventor： KREIFELS JERRY A , BAKER ALAN , HOEKSTRA GEORGE , KYNETT VIRGIL NILES , WELLS STEVEN , WINSTON MARK
Abstract: A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.
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公开(公告)号：GB2473149A
公开(公告)日：2011-03-02
申请号：GB201015976
申请日：2009-06-09
Applicant: INTEL CORP
Inventor： JUENEMANN DALE J , HOWES JORDAN , MATTHEWS JEANNA , WELLS STEVEN , HINTON GLENN , PINTO OSCAR P , TETRICK RAYMOND SCOTT
Abstract: In some embodiments, an electronic system may include a cache located between a mass storage and a system memory, and code stored on the electronic system to prevent storage of stream data in the cache and to send the stream data directly between the system memory and the mass storage based on a comparison of first metadata of a first request for first information and pre-boot stream information stored in a previous boot context. Other embodiments are disclosed and claimed.
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公开(公告)号：DE3900798C2
公开(公告)日：1995-05-24
申请号：DE3900798
申请日：1989-01-13
Applicant: INTEL CORP
Inventor： KREIFELS JERRY A , BAKER ALAN , HOEKSTRA GEORGE , KYNETT VIRGIL NILES , WELLS STEVEN , WINSTON MARK
Abstract: A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.
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公开(公告)号：GB2215155B
公开(公告)日：1992-07-22
申请号：GB8819579
申请日：1988-08-17
Applicant: INTEL CORP
Inventor： KREIFELS JERRY A , BAKER ALAN , HOEKSTRA GEORGE , KYNETT VIRGIL NILES , WELLS STEVEN , WINSTON MARK
Abstract: A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.
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