公开(公告)号：WO2005006412A3

公开(公告)日：2005-04-21

申请号：PCT/US2004019612

申请日：2004-06-18

Applicant: INTEL CORP

Inventor： GURUMURTHY CHARAN ,  AZIMI HAMID ,  LIN ARTHUR

IPC: H01L21/48 ,  H05K3/10 ,  H05K3/24 ,  H05K3/46

CPC classification number: H05K3/243 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4857 ,  H01L2924/00013 ,  H01L2924/0002 ,  H05K3/108 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2203/1572 ,  H01L2224/29099 ,  H01L2924/00

Abstract: A method of forming an integrated circuit substrate that may be adapted to be attached to one or more electronic components. The method includes applying a resist to a back side of a substrate which includes patterned conductive layers on a front side and a back side of the substrate. The method further includes removing part of the patterned conductive layer from the front side of the substrate to form pads and interconnects on the front side of the substrate and applying another resist to the front side of the substrate. The method also includes forming a pattern in each resist that exposes the pads on the front and back sides of the substrate and applying electrolytic nickel to the pads on the substrate.

Abstract translation: 一种形成集成电路衬底的方法，该集成电路衬底可以适合于附着到一个或多个电子部件。 该方法包括将抗蚀剂施加到衬底的背面，该衬底包括衬底的正面和背面上的图案化导电层。 该方法进一步包括从衬底的正面去除部分图案化的导电层以在衬底的正面上形成焊盘和互连并且将另一抗蚀剂施加到衬底的正面。 该方法还包括在每个抗蚀剂中形成图案，该图案暴露衬底的正面和背面上的焊盘并将电解镍施加到衬底上的焊盘。