公开(公告)号：JP2004349714A

公开(公告)日：2004-12-09

申请号：JP2004177959

申请日：2004-06-16

Applicant: Intel Corp ,  インテル・コーポレーションIntel Corporation

Inventor： SANKMAN BOB ,  AZIMI HAMID

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H05K3/34 ,  H05K3/46

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15312 ,  H05K3/3426 ,  H05K3/4602

Abstract: PROBLEM TO BE SOLVED: To provide a substrate joint technology in order to obtain electric, physical connection between external circuits in a multilayer substrate.
SOLUTION: A substrate 104 has a conductive viahole 126 prepared between isolated conductive layers. A viahole 124 is formed by laser in such a manner that it penetrates an insulator separating the conductive layers. Interconnection portion to exterior which consists of a T typeface pin is soldered to the substrate 104 of an integrated circuit package. An integrated circuit 102 can be adhered to the substrate by flip chip method.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种基板接合技术，以获得多层基板中的外部电路之间的电气物理连接。 解决方案：衬底104具有在隔离的导电层之间制备的导电通孔126。 通孔124通过激光形成，使得其穿透分离导电层的绝缘体。 由T字表面引脚构成的互连部分外部被焊接到集成电路封装的基板104。 集成电路102可以通过倒装芯片方法粘附到衬底。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：AU2003302851A1

公开(公告)日：2004-06-30

申请号：AU2003302851

申请日：2003-10-27

Applicant: INTEL CORP

Inventor： GUZEK JOHN ,  AZIMI HAMID ,  WOOD DUSTIN ,  MOBLEY WASHINGTON

IPC: H01L23/14 ,  H01L23/498 ,  H05K1/05 ,  H05K3/44 ,  H05K3/46 ,  H01L21/768 ,  H01L23/522

Abstract: Apparatus and methods are provided for a rigid metal core carrier substrate. The metal core increases the modulus of elasticity of the carrier substrate to greater than 20 GPa to better resist bending loads and stresses encountered during assembly, testing and consumer handling. The carrier substrate negates the need to provide external stiffening members resulting in a microelectronic package of reduced size and complexity. The coefficient of thermal expansion of the carrier substrate can be adapted to more closely match that of the microelectronic die, providing a device more resistant to thermally-induced stresses. In one embodiment of the method in accordance with the invention, a metal sheet having a thickness in the range including 200-500 mum and a flexural modulus of elasticity of at least 20 GPa is laminated on both sides with dielectric and conductive materials using standard processing technologies to create a carrier substrate.

公开(公告)号：WO0141212A3

公开(公告)日：2001-12-13

申请号：PCT/US0032904

申请日：2000-12-04

Applicant: INTEL CORP

Inventor： SANKMAN BOB ,  AZIMI HAMID

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H05K3/34 ,  H05K3/46 ,  H05K1/03

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15312 ,  H05K3/3426 ,  H05K3/4602

Abstract: An integrated circuit package is provided that includes a multi-layer organic substrate. The substrate has conductive vias provided between isolated conductive layers. The vias are formed using a laser to cut through a dielectric layer separating the conductive layers. External interconnects in the form of T-shaped pins are soldered to the substrate of the integrated circuit package. An integrated circuit can be attached to the substrate using a flip-chip technique.

Abstract translation: 提供了包括多层有机衬底的集成电路封装。 衬底具有设置在隔离导电层之间的导电通孔。 使用激光来形成通孔以切穿分隔导电层的介电层。 T形引脚形式的外部互连焊接到集成电路封装的衬底上。 集成电路可以使用倒装芯片技术连接到衬底。

公开(公告)号：WO2005006412A3

公开(公告)日：2005-04-21

申请号：PCT/US2004019612

申请日：2004-06-18

Applicant: INTEL CORP

Inventor： GURUMURTHY CHARAN ,  AZIMI HAMID ,  LIN ARTHUR

IPC: H01L21/48 ,  H05K3/10 ,  H05K3/24 ,  H05K3/46

CPC classification number: H05K3/243 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4857 ,  H01L2924/00013 ,  H01L2924/0002 ,  H05K3/108 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2203/1572 ,  H01L2224/29099 ,  H01L2924/00

Abstract: A method of forming an integrated circuit substrate that may be adapted to be attached to one or more electronic components. The method includes applying a resist to a back side of a substrate which includes patterned conductive layers on a front side and a back side of the substrate. The method further includes removing part of the patterned conductive layer from the front side of the substrate to form pads and interconnects on the front side of the substrate and applying another resist to the front side of the substrate. The method also includes forming a pattern in each resist that exposes the pads on the front and back sides of the substrate and applying electrolytic nickel to the pads on the substrate.

Abstract translation: 一种形成集成电路衬底的方法，该集成电路衬底可以适合于附着到一个或多个电子部件。 该方法包括将抗蚀剂施加到衬底的背面，该衬底包括衬底的正面和背面上的图案化导电层。 该方法进一步包括从衬底的正面去除部分图案化的导电层以在衬底的正面上形成焊盘和互连并且将另一抗蚀剂施加到衬底的正面。 该方法还包括在每个抗蚀剂中形成图案，该图案暴露衬底的正面和背面上的焊盘并将电解镍施加到衬底上的焊盘。

公开(公告)号：AT412974T

公开(公告)日：2008-11-15

申请号：AT00983895

申请日：2000-12-04

Applicant: INTEL CORP

Inventor： SANKMAN BOB ,  AZIMI HAMID

IPC: H01L23/00 ,  H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H05K3/34 ,  H05K3/46

Abstract: An integrated circuit package is provided that includes a multi-layer organic substrate. The substrate has conductive vias provided between isolated conductive layers. The vias are formed using a laser to cut through a dielectric layer separating the conductive layers. External interconnects in the form of T-shaped pins are soldered to the substrate of the integrated circuit package. An integrated circuit can be attached to the substrate using a flip-chip technique.

公开(公告)号：AU2059501A

公开(公告)日：2001-06-12

申请号：AU2059501

申请日：2000-12-04

Applicant: INTEL CORP

Inventor： SANKMAN BOB ,  AZIMI HAMID

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H05K3/34 ,  H05K3/46 ,  H01L23/00

Abstract: An integrated circuit package is provided that includes a multi-layer organic substrate. The substrate has conductive vias provided between isolated conductive layers. The vias are formed using a laser to cut through a dielectric layer separating the conductive layers. External interconnects in the form of T-shaped pins are soldered to the substrate of the integrated circuit package. An integrated circuit can be attached to the substrate using a flip-chip technique.

公开(公告)号：HK1046470B

公开(公告)日：2009-04-09

申请号：HK02107995

申请日：2002-11-02

Applicant: INTEL CORP

Inventor： SANKMAN BOB ,  AZIMI HAMID

IPC: H01L20060101 ,  H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H05K3/34 ,  H05K3/46

公开(公告)号：DE60040685D1

公开(公告)日：2008-12-11

申请号：DE60040685

申请日：2000-12-04

Applicant: INTEL CORP

Inventor： SANKMAN BOB ,  AZIMI HAMID

IPC: H01L23/00 ,  H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H05K3/34 ,  H05K3/46

Abstract: An integrated circuit package is provided that includes a multi-layer organic substrate. The substrate has conductive vias provided between isolated conductive layers. The vias are formed using a laser to cut through a dielectric layer separating the conductive layers. External interconnects in the form of T-shaped pins are soldered to the substrate of the integrated circuit package. An integrated circuit can be attached to the substrate using a flip-chip technique.

公开(公告)号：HK1046470A1

公开(公告)日：2003-01-10

申请号：HK02107995

申请日：2002-11-02

Applicant: INTEL CORP

Inventor： SANKMAN BOB ,  AZIMI HAMID

IPC: H01L23/12 ,  H01L20090101 ,  H01L21/48 ,  H01L23/498 ,  H05K3/34 ,  H05K3/46

Abstract: An integrated circuit package is provided that includes a multi-layer organic substrate. The substrate has conductive vias provided between isolated conductive layers. The vias are formed using a laser to cut through a dielectric layer separating the conductive layers. External interconnects in the form of T-shaped pins are soldered to the substrate of the integrated circuit package. An integrated circuit can be attached to the substrate using a flip-chip technique.