公开(公告)号：SG11201610647PA

公开(公告)日：2017-01-27

申请号：SG11201610647P

申请日：2015-06-19

Applicant: INTEL CORP

Inventor： RAUCHFUSS BRIAN D ,  MATAM NAVEEN R ,  DWYER MICHAEL K ,  NAVALE ADITYA

IPC: G06F9/30 ,  G06T1/00

Abstract: Methods and apparatus relating to mid-thread pre-emption with software assisted context switch are described. In an embodiment, one or more threads executing on a Graphics Processing Unit (GPU) are stopped at an instruction level granularity in response to a request to pre-empt the one or more threads. The context data of the one or more threads is copied to memory in response to completion of the one or more threads at the instruction level granularity and/or one or more instructions. Other embodiments are also disclosed and claimed.

公开(公告)号：EP3172660A4

公开(公告)日：2018-03-21

申请号：EP15823986

申请日：2015-06-19

Applicant: INTEL CORP

Inventor： RAUCHFUSS BRIAN D ,  MATAM NAVEEN R ,  DWYER MICHAEL K ,  NAVALE ADITYA

IPC: G06F9/30 ,  G06F9/46 ,  G06F12/1081 ,  G06T1/00

CPC classification number: G06F9/461 ,  G06F9/4812 ,  G06F12/1081 ,  G06F2212/2532

Abstract: Methods and apparatus relating to mid-thread pre-emption with software assisted context switch are described. In an embodiment, one or more threads executing on a Graphics Processing Unit (GPU) are stopped at an instruction level granularity in response to a request to pre-empt the one or more threads. The context data of the one or more threads is copied to memory in response to completion of the one or more threads at the instruction level granularity and/or one or more instructions. Other embodiments are also disclosed and claimed.