公开(公告)号：WO03096170A2

公开(公告)日：2003-11-20

申请号：PCT/US0310428

申请日：2003-04-02

Applicant: INTEL CORP

Inventor： CUI YING ,  SAMSON ERIC ,  BERKOVITS ARIEL ,  NAVALE ADITYA ,  WYATT DAVID ,  CLINE LESLIE ,  TSANG JOSEPH ,  BLAKE MARK ,  POISNER DAVID ,  STEVENS WILLIAM JR ,  SAR-DESSAI VIJAY

IPC: G06F1/04 ,  G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3215 ,  G06F1/324 ,  G06F1/325 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.

Abstract translation: 在本发明的一个实施例中，描述了一种集成装置，其采用机制来通过从时钟发生器接收的时钟信号的电压和频率调整来控制图形存储器控制器集线器（GMCH）的功率消耗。 GMCH包括图形核心和改变操作行为的电路，例如提供给图形核心的渲染时钟信号的频率。 该电路适用于监视图形核心的空闲，并且如果闲置时间超过确定的时间百分比，则降低渲染时钟信号的频率水平。

公开(公告)号：WO2004063916A2

公开(公告)日：2004-07-29

申请号：PCT/US2004000092

申请日：2004-01-02

Applicant: INTEL CORP

Inventor： SAMSON ERIC ,  NAVALE ADITYA ,  JENSEN SAM ,  SRITANYARATANA SIRIPONG ,  CHENG WIN

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3203 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: When a processor in a computer system is placed in a low power mode, power consumption of the computer system may be further reduced by reducing power consumption of one or more components of a memory coupled to the processor and by reducing power consumption of one or more components of a controller device coupled to the memory. The processor and the controller device may share the memory.

Abstract translation: 当计算机系统中的处理器被置于低功率模式时，可以通过减少耦合到处理器的存储器的一个或多个组件的功耗来降低计算机系统的功耗，并且通过减少一个或多个 耦合到存储器的控制器设备的组件。 处理器和控制器设备可以共享存储器。

公开(公告)号：DE102021122245A1

公开(公告)日：2022-03-10

申请号：DE102021122245

申请日：2021-08-27

Applicant: INTEL CORP

Inventor： CHAND NALLURI HEMA ,  SHAH ANKUR ,  RAY JOYDEEP ,  NAVALE ADITYA ,  KOKER ALTUG ,  RAMADOSS MURALI ,  COORAY NIRANJAN L ,  BOLES JEFFERY S ,  ANANTARAMAN ARAVINDH V ,  PUFFER DAVID ,  VALERIO JAMES ,  RANGANATHAN VASANTH

IPC: G06F13/14 ,  G06F7/00 ,  G06F9/30 ,  G06T1/20

Abstract: Offenbart wird eine Einrichtung zum Erleichtern von Speicherbarrieren. Die Einrichtung umfasst eine Zwischenverbindung, einen Vorrichtungsspeicher, eine Vielzahl von Verarbeitungsressourcen, die mit dem Vorrichtungsspeicher gekoppelt sind, um eine Vielzahl von Ausführungs-Threads als Speicherdatenerzeuger und Speicherdatenverbraucher an einen Vorrichtungsspeicher und einen Systemspeicher auszuführen, und Fence-Hardware zum Generieren von Fence-Operationen zum Durchsetzen einer Datenordnung bei Speicheroperationen, die an den Vorrichtungsspeicher und einen Systemspeicher ausgegeben werden, der über die Zwischenverbindung gekoppelt ist.

公开(公告)号：DE102015002366A1

公开(公告)日：2015-10-01

申请号：DE102015002366

申请日：2015-02-25

Applicant: INTEL CORP

Inventor： KOKER ALTUG ,  NAVALE ADITYA

IPC: G06F9/50 ,  G06F15/16

Abstract: Verfahren und Systeme können das Ausführen mehrerer Arbeitseinheiten durch einen physikalisch verteilten Satz von Rechen-Slices bereitstellen. Außerdem kann durch eine Cache-Fabric die Kohärenz einer oder mehrerer den mehreren Arbeitseinheiten zugeordneter Speicherzeilen über einen Graphikprozessor, einen Systemspeicher und einen oder mehrere Host-Prozessoren aufrechterhalten werden. In einem Beispiel verfolgen mehrere Kreuzschienenknoten die eine oder die mehreren Speicherzeilen, wobei die Kohärenz der einen oder der mehreren Speicherzeilen über mehrere Caches der ersten Ebene (L1-Caches) und über eine physikalisch verteilte Cache-Struktur aufrechterhalten wird. Jeder L1-Cache kann für einen Ausführungsblock eines Rechen-Slice vorgesehen sein und jeder Kreuzschienenknoten kann für ein Rechen-Slice vorgesehen sein.

公开(公告)号：EP3074866A4

公开(公告)日：2017-12-27

申请号：EP13898093

申请日：2013-11-27

Applicant: INTEL CORP

Inventor： COWPERTHWAITE DAVID J ,  RAMADOSS MURALI ,  SHAH ANKUR N ,  VEMBU BALAJI ,  KOKER ALTUG ,  NAVALE ADITYA

IPC: G06F9/46 ,  G06F9/455 ,  G06F9/50 ,  G06T1/20

CPC classification number: G06F9/45558 ,  G06F9/4555 ,  G06F9/5044 ,  G06F9/5077 ,  G06F2009/4557 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06T1/20 ,  G06T2200/28

Abstract: In an embodiment, a system includes a graphics processing unit (GPU) that includes one or more GPU engines, and a microcontroller. The microcontroller is to assign a respective schedule slot for each of a plurality of virtual machines (VMs). When a particular VM is scheduled to access a first GPU engine, the particular VM has exclusive access to the first GPU engine. Other embodiments are described and claimed.

公开(公告)号：SG11201610647PA

公开(公告)日：2017-01-27

申请号：SG11201610647P

申请日：2015-06-19

Applicant: INTEL CORP

Inventor： RAUCHFUSS BRIAN D ,  MATAM NAVEEN R ,  DWYER MICHAEL K ,  NAVALE ADITYA

IPC: G06F9/30 ,  G06T1/00

Abstract: Methods and apparatus relating to mid-thread pre-emption with software assisted context switch are described. In an embodiment, one or more threads executing on a Graphics Processing Unit (GPU) are stopped at an instruction level granularity in response to a request to pre-empt the one or more threads. The context data of the one or more threads is copied to memory in response to completion of the one or more threads at the instruction level granularity and/or one or more instructions. Other embodiments are also disclosed and claimed.

公开(公告)号：SG11201609130XA

公开(公告)日：2016-11-29

申请号：SG11201609130X

申请日：2015-06-04

Applicant: INTEL CORP ,  SURTI PRASOONKUMAR ,  NAVALE ADITYA ,  BOLES JEFFERY S

Inventor： SURTI PRASOONKUMAR ,  NAVALE ADITYA ,  BOLES JEFFERY S

IPC: G06T1/20

Abstract: Systems and methods may provide for receiving a plurality of signals from a software module associated with a shared resource such as, for example, an unordered access view (UAV). The plurality of signals may include a first signal that indicates whether a draw call accesses the shared resource, a second signal that indicates whether a boundary of the draw call has been reached, and a third signal that indicates whether the draw call has a coherency requirement. Additionally, a workload corresponding to the draw call may be selectively dispatched in a shader invocation based on the plurality of signals.

公开(公告)号：AT549680T

公开(公告)日：2012-03-15

申请号：AT07784526

申请日：2007-06-22

Applicant: INTEL CORP

Inventor： VEMBU BALAJI ,  NAVALE ADITYA ,  GANDHI WISHWESH A

IPC: G06F12/10 ,  G06F9/445 ,  G06F9/455 ,  G06F13/28 ,  G06T1/60

Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

公开(公告)号：DE602004024499D1

公开(公告)日：2010-01-21

申请号：DE602004024499

申请日：2004-01-02

Applicant: INTEL CORP

Inventor： SAMSON ERIC ,  NAVALE ADITYA ,  JENSEN SAM ,  SRITANYARATANA SIRIPONG ,  CHENG WIN

IPC: G06F1/32

Abstract: When a processor in a computer system is placed in a low power mode, power consumption of the computer system may be further reduced by reducing power consumption of one or more components of a memory coupled to the processor and by reducing power consumption of one or more components of a controller device coupled to the memory. The processor and the controller device may share the memory.

公开(公告)号：AT451644T

公开(公告)日：2009-12-15

申请号：AT04700069

申请日：2004-01-02

Applicant: INTEL CORP

Inventor： SAMSON ERIC ,  NAVALE ADITYA ,  JENSEN SAM ,  SRITANYARATANA SIRIPONG ,  CHENG WIN

IPC: G06F1/32

Abstract: When a processor in a computer system is placed in a low power mode, power consumption of the computer system may be further reduced by reducing power consumption of one or more components of a memory coupled to the processor and by reducing power consumption of one or more components of a controller device coupled to the memory. The processor and the controller device may share the memory.